EDO DRAM vs. SDRAM

Understanding the operation of Synchronous Dynamic Random Access Memory (SDRAM) is facilitated by first being familiar with Extended Data Out Dynamic RAM (EDO DRAM) operation, as there are similarities in the core operations of DRAM technology.
In a typical DRAM :
- There are four essential command pins: RASB, CASB, WEB, and OEB.
- When RASB transitions low with all command pins high, the DRAM internally enables the word line associated with the given address input at that time.
Following this:
- Upon the transition of CASB low, the DRAM enables the column select line (CSL) after a set period of time.
- To read data, the OEB pin must go low while the WEB remains high, and the data is then output on the DQ pin. The timing required is denoted as t-AA.
- When RASB returns high, the word line is disabled, and the sense amplifier is equalized.
Key AC parameters to keep in mind include t-RAS, t-RP, t-RC, and t-AA.
To read more data, a column command must be entered through CASB and OEB, along with the relevant address.
For data writing: - Wwb should be low, the desired data input is provided, and the OEB stays high. SDRAM introduces clock control into the process:
- Commands are synchronized with a clock signal, requiring precise timing for operations.
- DRAM designs must be capable of supporting various clock frequencies to operate efficiently.