Hello Sir Nice video I have a Question @6:41 you said that miller cap effect will change the value of the cap. It is a parallel plate cap & its formula is Cap=(k*area of parallel plate)/distance in parallel plate. Where k is constant. Cap does not depend on absolute voltage or direction of swing of voltage on the plates. I think you meant positive or destructive interference between the two signals due to the cap. Please comment . Regards Ankit
ankit mundra We are actually talking about miller theorem here. If I remember correctly, that parallel cap can be divided into two different caps whose values are dependent on gain of amplifier. That's why voltage will come into effect
Very precise and informative.. I have one question though. What is the reason for modelling via resistance as high in Cmax corner? It was found in your 14nm presentation
Hi document I am referring to is the global foundries 14nm digital design guidelines (Design methodology group) dated September 10 2013. The slide number is 07.
Excellent Video. Shed light on a few things I was wondering about. Well explained.
where did you dig up this guy? awesome explanation! thank you very much sir!
very informative video reg - 14 nm finfet.
thank you !
Hello Sir
Nice video
I have a Question @6:41 you said that miller cap effect will change the value of the cap.
It is a parallel plate cap & its formula is Cap=(k*area of parallel plate)/distance in parallel plate. Where k is constant.
Cap does not depend on absolute voltage or direction of swing of voltage on the plates. I think you meant positive or destructive interference between the two signals due to the cap.
Please comment .
Regards
Ankit
ankit mundra We are actually talking about miller theorem here. If I remember correctly, that parallel cap can be divided into two different caps whose values are dependent on gain of amplifier. That's why voltage will come into effect
Very precise and informative.. I have one question though. What is the reason for modelling via resistance as high in Cmax corner? It was found in your 14nm presentation
Hello @arun
May I know how can I access the presentation you are referring to ?
Hi document I am referring to is the global foundries 14nm digital design guidelines (Design methodology group) dated September 10 2013. The slide number is 07.