I have one question here. We will mainly focus on customer's requirement and try to deliver the timing models right especially the liberty models. Does customer again try to tweak around this voltage ? Is that where they call us back in ? What I understand you know we wont give the data across each process temperature and voltage , but only the worst cases. When the chip operates at any other conditions other than this qualified cases this problem may arise. Am i right here ?
where come this path slacks at chip level?during test of a chip??
I have one question here. We will mainly focus on customer's requirement and try to deliver the timing models right especially the liberty models. Does customer again try to tweak around this voltage ? Is that where they call us back in ? What I understand you know we wont give the data across each process temperature and voltage , but only the worst cases. When the chip operates at any other conditions other than this qualified cases this problem may arise. Am i right here ?
Intel should of call this guy in on 10nm. I bet they had a ton of problems with process variation.