Introduction to SV-UVM RAL(Register Abstraction Layer).

[@shyamt5525]

Thanks for making the video. I found it useful for getting basic info on UVM RAL. Thanks!

[@gokulp6878]

Concepts are clearly explained in this excellent explanation

[@fathimakamrudeen9380]

Very well explained, thanks alot.✨

[@215_raveenchandra8]

Excellent job sir ...

[@venkateshmandavilli2074]

Well explained. Can you also post a video on the driver sequencer connection. It's a bit confusing. Thanks

[@MunsifMAhmad]

It's very easy bro ..
Just google driver and sequencer connection u will find one block dig, goto www.testbench.in image see the first block dig, driver has an inbuilt port(seq_item_port) where as u will find sequencer has an inbuilt export(seq_item_export)and connection will start from drivers bcz it's an initiator hence in the connect phase of agent u will find the below line of code map this with that block diagram u will get a clear picture.
drv_h.seq_item_port.connect(seqr_h.seq_item_expot);
drv_h is driver class object and seqr_h is sequencer class object.
I hope this information will help :)

[@bhanuvikas8348]

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[@NIKHILR-s7p]

Hi i am new uvm and ral , can we do ral without apb interface

[@omairkhan1355]

Munsif, will you please create an invironment, where we have couple of registers and memory and then explain. That will be very helpfull for us. Because people who wants to learn RAL they are already familiar with UVM, SV, VERILOG.

[@MunsifMAhmad]

Will try, Appreciate your suggestion. Thanks:)

[@hassanilyas7874]

Any example?

[@gokulp6878]

can you please explain about uvm_config_db and uvm_resource_db

[@MunsifMAhmad]

Yes , I will make one video on this topic..

[@gokulp6878]

@@MunsifMAhmad thanks

[@bhanuvikas8348]

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