SoC 101 - Lecture 6b: Cache Organization

System-on-Chip 101
or
"Everything you wanted to know about a computer but were afraid to ask"
This is Lecture 6 of my "SoC 101" course at Bar-Ilan University. In this course, I provide an overview of computer hardware engineering and SoC design, covering the full stack from the basic terminology, through computer architecture, and up to low-level software and design methodologies. The purpose of this course is to methodologically tell you about all those things that you may not have heard during your engineering studies and "fill the gaps" between the parts that you learned in-depth. It is in no way intended to provide a full, detailed description of every concept introduced, but following the course will give you a good idea about how a computer or any embedded system actually works.
Lecture 6 is all about the memory hierarchy, focusing on caches and virtual memory. The lecture starts with the motivation for having a memory hierarchy and the principles of locality (spatial and temporal). It then dives into caches, explaining how they operate, the parameters that affect their performance, and tradeoffs in cache design. After that, the concept of virtual memory is introduced, going into the details of how it works, its challenges and how they are dealt with. The lecture finishes with the introduction of the TLB, how it all fits together within the CPU pipeline, and the various addressing possibilities of caches with TLBs (PIPT, VIVT, VIPT).
Lecture slides can be found on the EnICS Labs web site at:
enicslabs.com/academic-course...
All rights reserved:
Prof. Adam Teman ‪@AdiTeman‬
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[@gamar1226]

Very nice series as usual :D . I was wondering how can I get better at chip design? I will start working this monday as a deisgn verification junior after I completed my internship but want to dive more deeply into full chip workflow. I was thinking of trying to go through the OpenLane documentation and try to take a full design and go through all the steps in the workflow until I get a GDSII file.

[@AdiTeman]

This sounds like a good methodology.
The EDA vendors also provide educational kits on their support sites, which are generally open to academia and industry (sometimes for a fee). I hope in the future to be able to collaborate with some of them to provide such tutorials here, on my RUclips channel, but this probably won't be relevant for you :)