STA lec15 defining input-output constraints part 1 | static timing analysis tutorial | VLSI

[@zezozezo5103]

Very informative thank you

[@truptichauhan3634]

Very informative content

[@manjunathr9680]

Thanks sir , nice and clear explanation .

[@rashmits1834]

Thank you so much sir🙏🙏🙏

[@rashmits1834]

@@VLSIAcademyhub definitely sir

[@sanjayganesh2079]

What will be the setup time for a D flop if the output of the same flop is connected to the d input of same flop (feedback loop)??

[@padmajmanore8886]

I have one doubt, for source latency why arent we referring clk instead of CLK? isn't it like [get_ports clk]?? Also thank you so much for this lecture series

[@avulamanojkumarreddy9971]

what is the difference between get_clocks and get_ports ? and when we use them