STA lec13 defining constraints | static timing analysis tutorial | VLSI

#vlsi #academy #sta #setup #hold #VLSI #electronics #semiconductor #cell #delay
This video describes about how logical drc constraints are defined. It describes in detail with examples that how is it calculated and specified in design. Must watch not only for beginners but also for professionals for refreshing the concepts.

[@vivekartist6893]

wonderful explanation! Thanks, you guys are helping me to prepare for interviews in a quick and easy manner!

[@VLSIAcademyhub]

Our pleasure!

[@shri1527]

great content and explained in very simple manner.thank you. I would like know the real application of contraints file in a vivado project. Once if i write down the RTL, I usually give port pin connection to the variables i use in RTL inside the constraints . (=IO mapping). In FPGA how do we create contraint file and where do we have std lib file in it?

[@shri1527]

@@VLSIAcademyhub could you give us a demo where you write RTL and find out the maximum acceptable frequency which also include your configurable constraint file? I would appreciate your efforts.

[@tamilabhivlog9473]

Thanks sir for the video

[@rashmits1834]

Superb sir... Thank you

[@stendall]

Which STA tool are you referring to in the video? OpenSTA?

[@shri1527]

could post more constraint apart from transition and load