System Verilog Tut 8 | Object Oriented Prog. Encapsulation

[@hemantrajyora6965]

Well explained bhai

[@MuhammadShahzad-dx5je]

Very nice explanation sir.

[@vlsichaps]

Thanks and welcome, Keep watching..

[@manikantabaratam589]

Encapsulation is really appended for class members or class methods also?

[@gunjanpandey2585]

Will same name 'c' for variable and class not create conflict or error..?

[@hemantrajyora6965]

if class properties and class methods have same name properties then you can differentiate between them using this keyword.

[@hemantrajyora6965]

as method can access variables outside it so conflict with variable having same name properties but doesn't give error

[@virajpadwal7624]

Sir more videos on UVM please

[@sewanjaliroy6847]

Can you make video for every topic in sequence for system verilog

[@sewanjaliroy6847]

Bcoz no one had made complete video so I think most of the people will watch it

[@prathibhack1546]

can we access a protected variable inside the top module

[@hemantrajyora6965]

only access to extend class but not outside class not even inside module .

[@hemantrajyora6965]

@ 07:00 use can see here