SystemVerilog Scheduling Semantics

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  • Опубликовано: 15 янв 2025

Комментарии • 2

  • @vinodsake
    @vinodsake 7 лет назад

    If we mention input #delay, it means that scheduler should schedule delay time before the clocking event occurs. So input #5 should be sampled at #165. but why is it scheduled at #170?

    • @narendrak2974
      @narendrak2974 3 года назад

      may be one posedge #5 and neg edge #5 becomes 10 units