FPGA - 06, Quartus and ModelSim: Verilog and Test Bench

insert these code to the test bench file:
--------------
initial
begin
clk = 1'b0;
#100 reset_n = 1'b0;
#100 reset_n = 1'b1;
#100 select = 1'b0;
#3000 select = 1'b1;
#4000
$stop;
end
always
begin
//Clock generator
#5 clk = ~clk;
end

[@gabizman]

First good tutorial i saw ! and i'm french

[@samborms]

good video, because Quartus and ModelSim are two different programs they have to connect, but the official information it was fragmented this video shows all in one, thank for your time making this video

[@robertopompa7765]

You are the best chinese boy, TEEIII

[@robertopompa7765]

TEEEEEEEEEEEEEEEI