IMPLEMENTATION using STATIC CMOS, DYNAMIC CMOS, PSEUDO NMOS, TG, CCMOS, PULLUP &PULL DOWN
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- Опубликовано: 24 сен 2024
- 𝗗𝗢𝗪𝗡𝗟𝗢𝗔𝗗 𝗦𝗵𝗿𝗲𝗻𝗶𝗸 𝗝𝗮𝗶𝗻 - 𝗦𝘁𝘂𝗱𝘆 𝗦𝗶𝗺𝗽𝗹𝗶𝗳𝗶𝗲𝗱 (𝗔𝗽𝗽) :
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I have exam tomorrow for VLSI and watching this video. A great help. Thanks bro. You saved time.
Same here, before watching this video I was planned to skip these questions in exam.
I was also preparing today wanted to learn this somehow and finally this opened the way
And history repeats itself again
10th of March 10:30
Bhaii or kya kya kiya bata jara
I wish our faculties of college could able to explain like this. simple and quick.
Amazing bro🙌
Explanation is in simple words, clearly understandable, a like and a comment is not sufficient to appreciate u, keep moving...waiting fr more videos of u
kumar Awesome
Thanks for supporting 🙂
Do share with your friends too 🙂
Very unique information not there in any videos, superb sir 🎉🔥🔥🔥🔥
VLSI tomorrow and was going this skip this part in exam. But i think when your teacher is shrenik jain then it's impossible for you to skip anything.
Can u please do this too Realize the expression for AND gate using the following logic style.
1. Clocked CMOS logic 2. Pseudo NMOS
3. Dynamic PMOS
4. Domino Logic
So what is the difference if you're given for example Y=(A*(B+C)) instead Y=(A*(B+C))' ?
yes, that is the error in this video
transmission gate isn't correct, because, there are cases in which output is floating, and it doesn't have any value.
Finally someone who explains this ish well. Why is it so mfckin hard to find good videos on this subject? electronics and computer science is literally the most studied subject in the world
:)
Clear explanation is what we need and you have done the best.♥️
what would be static cmos circuit for (abcd)'
Thank you for explaining in simpe manner which we get in easier way .. and not in the college also
bro I got question ..Design 3 input CMOS OR and AND inverter..what does it mean? CMOs OR* Nand..... or CMOS NOR *Nand?.......or Drawing sepatetly CMOS OR ,CMOS And?
why the clock and "X" network are in series in the dynamic CMOS?
Great job man but there is one mistake I think. for the dynamic CMOS circuit only the Pull Down Network is used and the Pull Up part is not used. Overall nice explaining and keep it up :)
Abdelhamied Raslan
Both are present..
As per what I have studied
Shrenik Jain the pmos part is not present
Yes. In dynamic CMOS logic PUN is not present only PDN is used.
I was searching this all the day .
This is the only video in you tube which makes it so simple. ♥️
OMG these Tricks Are Awesome Bro.May the RUclips Algorithm Help You and God bless You.Please Post More Gate Cse Vedios
bro trust me when I say you're the teacher we all want
In dynamic CMOS I don't think pmos part exists as it's mentioned in my book and everywhere on internet also please clarify my doubt.
Technical Anatomy
What u r saying is -
dynamic pull down circuit
yes pmos is not present . only PDN and 2 clocks
right!! there is no pmos block in dynamic cmos design
Same doubt.. And tmrw is my VLSI exam.. Can anyone clear this doubt..?
@@anandjk7733 yes i can, pmos block is not there. Hope your test goes well. Good Luck.
Which is better and why -cmos nand gate or cmos nor gate??
what if 3 variables are present in case of transmission gate implementation ??. for ex. if the expression is AB + A'B'+AB'C
first get the output by 2 variable then apply it to another TG input and the 3rd variable to the nmos gate of the 3rd TG.
What if we don't have a complement on the entire function? For eg. if the function is AB+CD+EF?
Also, how to do if individual terms have complement? for eg. AB'+C
Bidisha Das
Use demorgan law
Bidisha Das
For ur first question, make it double complement. i.e. (AB+CD+EF)''
Then put a inverter in the output of (AB+CD+EF)'
So, in final output u get the final result.(AB+CD+EF)
use a TG with input =A and put B' at the nmos gate of the TG.Take the output of this TG and combine it with C and get the output line from this.
Fantastic! This video helps a lot for quick revision... keep it up bro...
how do you draw stick diagram for pseudo nmos logic
while Implementing TGL lastly you added a not gate which is a digital one .Doubt is we have to add a inverter right ??
Can you please do transistor sizing for static CMOS
i think you forgot the inversor at the output of the circuit
Thank you soo much , very clear and nice explanation
+CircuitsMadeEasy
Welcome 😃
Can you please draw a stick diagram for the same expression
Really bhai very important and helpful video
thank you very much....
Welcome 😃😊
Great Work Bro.. Really Helpful... Post more such type of videos
sauravmohapatra
Sure 😃
Share with your friends too 🙂🙂🙂
Everything is clear now😀😀 thank you for this🙏🙏.
"It seems that your concepts are impeccably great.It was a great help.Will recommend"!
Keep learning keep sharing 😊
There is no Pseudo NMOS explaination
12:28 Hey in transmission gate. Shouldnt we use OR gates to add the outputs
what about the implementation of Domino cmos ? Is the any similarities between domino and the above mention logics ? plz help
A LOT OF THANKS BECAUSE OF UR VIDEOS VLSI WILL BE CLEARED AAJ KA PAPER WAS SET BY SEEING UR VIDEOS THINK SO . 🤩
😎😃
how to implement (AB +BC )' bplz explain
Thank u so much for helping us sir n d transmission gate logic was so easy to understand bcz of u .
welcome :)
Saved me a load of hustle for my VLSI final.
Where's the PTL one though? 🤔
#DWH
thnx man! worth the 13 minutes.
+NISHANT KUMAR BARUA 15BEC0567
Welcome 😃
Share with your friends too 🙂😃
Plz give a lecture on bicmos technology
What does Pseudo NMOS means? What's the difference with others?
Bhai paas krva diya apne :-)
The best explanation ever. Love love love.
TY :)
nice video,bro tmrw i have digital ic design exam -Thank you very much
bro have you made any video for full adder using cmos
what if the equation dont have a bar...
Cool!!!!!
Thnks.....
Thankyou very much
For such understandable explanation
Welcome 😃😊
What is name of video starting tune
Can you show Bicmos logic implementation of this function?
Excellent bro💥💥
great explanation. THANK YOU so much !!
Thanks for your superb tutorial
+Shovo Shuvo
Welcome 😃
Share with your friends too 🙂
Awesome brother....Simply awesome
Ty 😄😊
Share with your friends too 🙂
Amazing bhai Mera paper hai kal samjha ab 8 Mark mere😂😂
How to draw gate using resistive load?
Super well explained, thanks!
welcome :)
Hey where is PTL implementation?
Thanks man..you doing great work !👍🏻
I did the questions of tg using the trick but the teachers has cut the marks saying this method is wrong... Now what to do
You are a life saver!
yaar paper clear kara diya aapne.. thanks
Welcome 😃
Ashutosh Rogye hello frand, thoda padh lo
very very good explanation. thanks bro!!!
SUBHASRI BANERJEE
Ty 😄😊
this video is gold
very nice bro
very important video. thank you!
jal
Welcome 😃
I think..In dynamic cmos pmos component will not be present .
Bro , plzz do a lecture on XNOR GATE and XOR GATE in NMOS and CMOS technologies. Hope u do so..
Awesome video... very helpful
Ayush Labh
Thanks man 😃.
Do share with your friends too 🙂🙂
There is no PMOS block present in Dynamic Logic.
This was really helpful! Thanks 😊
welcome :)
glad you liked it !!
do share with your friends too :)
Sure! 👍
Sir do you teach for gate ece where to get your course
How about (AB + C (A+B))'
thank you so much.. very helpful
Hinduja 7
Welcome 😃
Share with your friends too 🙂
A really really great explaination bruh🔥helped alot
It was very helpful.. thank you
+upasana hazarika
Welcome 😃
Share with your friends as well 😊
Thank you👍
simple and easy :)
Thanks for such great teaching
Welcome 😊
Can you plze put videos on MOSFET fabrication
Have u not solved PTL as mentioned???
Awesome Broo...loved ur videos..1 subscription earned😀✌
THANKS MAN U DA BEST
Srujan Hunkzz
Thanks 😃
Share with your friends as well 😊
Nicely explained!
Ty 😄😊
last minute engineers thanks you !
Dude you're the best
Ty 😊
Thank you so much bro!
That trick was great 🔥
very good explanation
Bahot badhiya bhai
Omkar Dixit
Thanks 😃
Share with your friends as well 🙂
Thanks bro it was very helpful
Welcome 😇
Great video bro
ty :)
share with your friends too :)
Keep it up!
M confused..on which circuit v have to put a not gate in front and on which v don't have to?
i mean the entire circuit..only for the last circuit we have added a not gate in front ..is it because for the rest of the circuits excluding TG logic circuits the output is in the complemented form?
Those circuit which needs the complimentary output,not gate is used.
Thanks
dynamic CMOS is so wrong theres no PMOS ckt only one with clock input
You are right 👍 good that someone noticed it
sir when I fill the form it gives that your response has record and submit another response how to get the pdf
Very good explanation. We teachers are also biased.GREAt
"This is A , this is B
Both are parallel to each other as you can see".
What a pun 😂
Anyway dude, the explanation was amazing. Thanks for the video.was exactly in the search of it
hahaaha; proof that you have intensely concentrated!!
whole course in 1 vedio
Super easy sir