The timestamps for the different topics covered in the video: 0:45 what is Step Size, Resolution and Full-scale output voltage of DAC? 6:19 Binary Weighted Resistor DAC ( 3 -Bit DAC example) 14:50 Binary Weighted Resistor DAC limitations (with example)
After attending hours of hours boring lectures I don't understand the DAC what i have understand from this video. By truly speaking you are better than the college teachers, who always chanted by the name of teaching us digital electronics.
I was wondering how does the DAC reach the smooth (not staircase) output? Because of the lowpass filter before the ADC sampling, from the sampled signal the orignal low passed signal can be fully (smoothly) reconstructed (no staircase) as is proven by the Fourier transforms. Therefore if I had to design a DAC I would create the smooth output by either digitally oversampling and interpolating and low pass filtering.
Excellent presentation again, but I have a question. Couldn’t we achieve a similar result with a binary weighted resistor network alone. Why do we need an op amp?
The obvious advantage of the op-amp is high input impedance and low output impedance. Apart from that, the concept of the virtual ground is very handy over here. Because whenever the bits which are logic low or 0, their resistor will be grounded. And won't affect the other inputs. Without op-amp when all the resistors are directly connected in parallel, then the resistors whose input value is logic zero will also affect the other inputs And will change the overall output. That's why op-amp is required. I hope it will clear your doubt.
in the above you said resolution and step size are same but they are different.....resolution is inverse of no of steps......where as stepsize is ref voltage by total no of steps
If you consider the reference voltage then the resolution is Vref / 2^n. If you consider the full-scale output voltage (FSO) then it is FSO / (2^n -1). Basically, FSO is 1 LSB less than the Vref. I hope it will clear your doubt.
At 7:09, I have mentioned the expression of inverting summing amplifier with three inputs. Now, in this expression, suppose, V1 = V2 = V3 = Vref, then you will have Vref x Rf common in the expression, right !! I hope, you will get the point. For more info, you can watch the video on summing amplifier using the op-amp. I have already provided the link for the same in the description. And here is the link : op-amp as a summing amplifier ruclips.net/video/jsKSfaFQ4d4/видео.html
The F.S.O shown in the transfer function is for different case ( It is for the case which I have discussed at the beginning, when resolution of 3 bit DAC is 0.625 V). In this case, it is double. I have also mentioned that just after that. I hope, it will clear your doubt.
You said on increasing resolution, we can reduce stepsize ,but the step size it self is the resolution? I couldn't get that point ...what is the relation between them 1:57
What you are saying is true, but here I am referring to the steps seen in the output waveform (In yellow color) as a step size. So, if we increase the resolution, then the output waveform will be much close to the actual waveform and the steps seen in the output waveform will reduce. I hope, it will clear your doubt.
For the given 3 bit DAC at 3:22, When your input code to DAC is 000 then the output voltage is 0V. When input code is 001, then the output code is 5/8V. And Likewise, when the input code to DAC is 010 then output voltage is 10/8 volt. You will not be able to generate the voltages in between. I hope, it will clear your doubt.
The op-amp serves two purpose. It act as a buffer between the input and output side. And second, it also performs the summing operation. And because of the op-amp, if required then it is also possible to provide additional gain by changing the feedback resistor.
Is it possible to have lower output voltage after using op amp in magnitude in full scale output case in comparison to its input vref of 5v? During weighted resistor during formula we can extract that resolution is Vref/(2^(n-1)) not Vref/2^n. There are many other resources they talk the same but in your it’s different. I am talking in zero based configuration.
I think you are taking about having FSO lesser than Vref, right !! Well, if so, then yes using the op-amp, it is possible to have that. In fact, if you see many DACs, then they have different operating voltage range (even with same Vref)
Initially, assuming ideal resistors, the the value of 1LSB was calculated. And then for 1% tolerance the maximum and minimum value of Vo was found. In reality, we will not have ideal resistors in the DAC. There will be some tolerance. But by doing the theoretical calculation for ideal resistors, gives us an idea about the expected output voltage.
Hi. During problem solving corresponding to this video, Why Lsb (B0), used to the left most corner.. It should be to the taken to the right most corner..... Ex 10 here "1" is my MSB and "0" is my LSB.. Right? .. I saw in video it was opposite.. Plz hlp
Sir i've question. Are MSB and LSB in weighted resistor binary determined by the highest and lowest value of resistors or by the position of resistors?
You can identify them from the resistor value. The resistor at the LSB position will have highest resistance value, while the resistor at the MSB position will have lowest resistor value.
In general for n -bit DAC, percentage resolution is 1x 100 / (2^n - 1). For more information, please check this video. ruclips.net/video/QPJRXIUPVGw/видео.html
with a non-inverting configuration, you won't get the expression of the Vout in the binary-weighted form. Because Vo = (1 + Rf/ R1)*Vin I hope it will clear your doubt.
The resolution (in volts) depends on how it is calculated. Considering the reference voltage, it is Vref/ 2^n. But if you consider the full-scale output voltage (FSO), then it is FSO / 2^n - 1.
With Rf = R, when all bits are 1, the output is 2*Vref ( 2^n -1) / 2^n Or in this case, Vo is 5*64/32. So, it is more than reference voltage. So, depending on DAC type, the Full Scale Output Voltage can be more than reference voltage. (I am just consiering the magnitude of the voltage). For DAC, the supply voltage may be a different from reference voltage. And hence output can be greater than the reference voltage, depending on the structure of DAC. Please watch couple of mins of the introduction of the video, it will get clear to you. And if you still have any doubt, then let me know here.
1:53 Does increasing resolution decreases step size???? For that I doubt that we have to reduce resolution(by decreasing reference voltage or by increasing number of bits) ????????????
For resolution, the lower is better (the absolute value in mV or V). Its the smallest increment in the output that DAC can produce. Of course, as you said, it depends on the reference voltage and no. of bits. So, typically, when the two ADC or DAC are compared in terms of resolution, then they are compared in terms of no-of bits. And higher the number of bits, the better is the resolution of the ADC or DAC. If you see, in terms of mV or V then absolute value reduces with increasing no. of bits (and so does the step size). I hope, it will clear your doubt.
The timestamps for the different topics covered in the video:
0:45 what is Step Size, Resolution and Full-scale output voltage of DAC?
6:19 Binary Weighted Resistor DAC ( 3 -Bit DAC example)
14:50 Binary Weighted Resistor DAC limitations (with example)
sir hindi me important topic explain kr lete
After attending hours of hours boring lectures I don't understand the DAC what i have understand from this video. By truly speaking you are better than the college teachers, who always chanted by the name of teaching us digital electronics.
Dude same here
this is the clearest video i've ever seen before. thank you sir
Very Nicely explained sir, the detailed explanation is amazing 👌
good videos. Play at 1.5x speed.
thanks so much for this explanation! 😊
The LSB initially you said was vref/(2^n) ffor DAC and then you said it is vref/[(2^n) -1)] for weighted. why is that
Superb explanation dada 👍👍
I was wondering how does the DAC reach the smooth (not staircase) output? Because of the lowpass filter before the ADC sampling, from the sampled signal the orignal low passed signal can be fully (smoothly) reconstructed (no staircase) as is proven by the Fourier transforms. Therefore if I had to design a DAC I would create the smooth output by either digitally oversampling and interpolating and low pass filtering.
Excellent videos. can you please tell what tools you are using for digital writing? I am also teaching online classes to my students
Its a digital writing pad,Mostly a wacom digital pad
nice explained!
Appreciate so much
Please Check 12.19 you write FSR of Ladder Type Resistor DAC , Instead Of Binary Weighted Resistor DAC FSR , check and rectify it ..
fantastic .. keep it up
God bless you
Excellent presentation again, but I have a question. Couldn’t we achieve a similar result with a binary weighted resistor network alone. Why do we need an op amp?
The obvious advantage of the op-amp is high input impedance and low output impedance. Apart from that, the concept of the virtual ground is very handy over here. Because whenever the bits which are logic low or 0, their resistor will be grounded. And won't affect the other inputs.
Without op-amp when all the resistors are directly connected in parallel, then the resistors whose input value is logic zero will also affect the other inputs And will change the overall output.
That's why op-amp is required.
I hope it will clear your doubt.
ALL ABOUT ELECTRONICS Thank you that helped.
Thanks a lot 🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏
Thank for the video
Thanks, but can you tell how R is formed? I am confusing here.
in the above you said resolution and step size are same but they are different.....resolution is inverse of no of steps......where as stepsize is ref voltage by total no of steps
here when we converting from binary to analoge what is acthually need of dividing by 1248
Very nice
Sir in some book they mentioned resolution as Vref / ( 2^n - 1 ), which one is correct. please reply.
If you consider the reference voltage then the resolution is Vref / 2^n.
If you consider the full-scale output voltage (FSO) then it is FSO / (2^n -1).
Basically, FSO is 1 LSB less than the Vref.
I hope it will clear your doubt.
@@ALLABOUTELECTRONICS Thanks. so basically step size is the resolution of signal ?
@@vijayakumarr3519 Step size is basically a resolution of the ADC or DAC.
Hello Vijay, resolution = range/( 2^n)-1
Sir, why reference voltage product with feedback resistance in summing amplifier output voltage expression?
At 7:09, I have mentioned the expression of inverting summing amplifier with three inputs. Now, in this expression, suppose, V1 = V2 = V3 = Vref, then you will have Vref x Rf common in the expression, right !!
I hope, you will get the point.
For more info, you can watch the video on summing amplifier using the op-amp.
I have already provided the link for the same in the description.
And here is the link :
op-amp as a summing amplifier
ruclips.net/video/jsKSfaFQ4d4/видео.html
thankyou
Thank you sir
In which case, Full scale output equals reference voltage?
When measuring the output with a 4bit DAC, Vref=5V, and R1=Rf=1kohm ,R2=2,R3=4,R4=8. What is the result of max = 6V?.Thank3
12:56
The value of the F.S.O. is -35/8 you wrote it -35/4.
The F.S.O shown in the transfer function is for different case ( It is for the case which I have discussed at the beginning, when resolution of 3 bit DAC is 0.625 V). In this case, it is double. I have also mentioned that just after that. I hope, it will clear your doubt.
keep going plz.
Thanks for this. I will like to ask, what formula was use to calculate the Vout for the transfer function plotting itself.
Its step size x Digital count.
You said on increasing resolution, we can reduce stepsize ,but the step size it self is the resolution? I couldn't get that point ...what is the relation between them 1:57
What you are saying is true, but here I am referring to the steps seen in the output waveform (In yellow color) as a step size. So, if we increase the resolution, then the output waveform will be much close to the actual waveform and the steps seen in the output waveform will reduce. I hope, it will clear your doubt.
Shouldn’t the x and y labels be flipped???? 3:22? Because that means for even .00001 V the binary o/p will be 001
For the given 3 bit DAC at 3:22, When your input code to DAC is 000 then the output voltage is 0V. When input code is 001, then the output code is 5/8V. And Likewise, when the input code to DAC is 010 then output voltage is 10/8 volt. You will not be able to generate the voltages in between. I hope, it will clear your doubt.
sir what is the need of using a op amp here can not we only use the resistent network only
The op-amp serves two purpose. It act as a buffer between the input and output side. And second, it also performs the summing operation. And because of the op-amp, if required then it is also possible to provide additional gain by changing the feedback resistor.
Is it possible to have lower output voltage after using op amp in magnitude in full scale output case in comparison to its input vref of 5v? During weighted resistor during formula we can extract that resolution is Vref/(2^(n-1)) not Vref/2^n. There are many other resources they talk the same but in your it’s different. I am talking in zero based configuration.
I think you are taking about having FSO lesser than Vref, right !! Well, if so, then yes using the op-amp, it is possible to have that. In fact, if you see many DACs, then they have different operating voltage range (even with same Vref)
Hello Sir, is Binary Weighted Resistor DAC also known as " Binary Ladder Network "
Is there a simple design to make the control switch?
MOSFET can be used as a switch. MOSFET based switches are readily available in the IC form.
@@ALLABOUTELECTRONICS Is that the fastest option? again, should we use like two cmos inverters as switch?
why are u donit multiple the binary weighted by 1\2
@ 17:40 How do you know when the resistor is ideal?
Initially, assuming ideal resistors, the the value of 1LSB was calculated. And then for 1% tolerance the maximum and minimum value of Vo was found. In reality, we will not have ideal resistors in the DAC. There will be some tolerance. But by doing the theoretical calculation for ideal resistors, gives us an idea about the expected output voltage.
@@ALLABOUTELECTRONICS Thankyou for explaining
Please upload 9400 v to f converter
Hi. During problem solving corresponding to this video, Why Lsb (B0), used to the left most corner.. It should be to the taken to the right most corner..... Ex 10 here "1" is my MSB and "0" is my LSB.. Right? .. I saw in video it was opposite.. Plz hlp
Was referring to this time 13:35
Sir i've question. Are MSB and LSB in weighted resistor binary determined by the highest and lowest value of resistors or by the position of resistors?
You can identify them from the resistor value. The resistor at the LSB position will have highest resistance value, while the resistor at the MSB position will have lowest resistor value.
What is the voltage of 16 bit on transistors
Can anyone pls tell me ref voltage is same or not
We can use 16 bits with one resistor
how
What is the percentage resolution of 4 bit DAC????
In general for n -bit DAC, percentage resolution is 1x 100 / (2^n - 1).
For more information, please check this video.
ruclips.net/video/QPJRXIUPVGw/видео.html
Why don't we use non inverting opamp configuration??
with a non-inverting configuration, you won't get the expression of the Vout in the binary-weighted form.
Because Vo = (1 + Rf/ R1)*Vin
I hope it will clear your doubt.
sir i think you defined resolution wrongly ..............in gate academy i saw resolution is 1/(2^n - 1)
The resolution (in volts) depends on how it is calculated. Considering the reference voltage, it is Vref/ 2^n.
But if you consider the full-scale output voltage (FSO), then it is FSO / 2^n - 1.
u say that the output v must be less than the refrence v by 1LSB
The full scale output voltage is 1 LSB less than the reference voltage.
namaste Sir ,@17.42 how Vout is less than vref
With Rf = R, when all bits are 1, the output is 2*Vref ( 2^n -1) / 2^n
Or in this case, Vo is 5*64/32.
So, it is more than reference voltage.
So, depending on DAC type, the Full Scale Output Voltage can be more than reference voltage. (I am just consiering the magnitude of the voltage).
For DAC, the supply voltage may be a different from reference voltage. And hence output can be greater than the reference voltage, depending on the structure of DAC.
Please watch couple of mins of the introduction of the video, it will get clear to you.
And if you still have any doubt, then let me know here.
@@ALLABOUTELECTRONICS i still doubt
@@ALLABOUTELECTRONICS u say that v out must be less than v ref by 1 LSB
@@ALLABOUTELECTRONICS and in this case the result of (fso/(2^n)-1) not equal (v ref/2^n)
אני פה בגלל אורט בראודה הפח אשפה
1:53
Does increasing resolution decreases step size????
For that I doubt that we have to reduce resolution(by decreasing reference voltage or by increasing number of bits) ????????????
For resolution, the lower is better (the absolute value in mV or V). Its the smallest increment in the output that DAC can produce. Of course, as you said, it depends on the reference voltage and no. of bits. So, typically, when the two ADC or DAC are compared in terms of resolution, then they are compared in terms of no-of bits. And higher the number of bits, the better is the resolution of the ADC or DAC. If you see, in terms of mV or V then absolute value reduces with increasing no. of bits (and so does the step size).
I hope, it will clear your doubt.
@@ALLABOUTELECTRONICS Sir so you mean to reduce absolute value (resolution) in video???????????? In order to decrease step size.??
Yes.
12:09
Thank you very much Mr can you send to me your email or facebook
Poor presentation
shut up and go away
Thank you sir