The Design of Two-Stage Miller Op-Amp: The Final Verdict! | Dr. Hesham Omran

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  • Опубликовано: 2 авг 2024
  • Live talk and slides link: / omranh_two-stage-ampli...
    The two-stage Miller op-amp is a circuit for all seasons. It is there in almost every analog IC design course and every analog/mixed-signal chip. But despite being an ubiquitous circuit, there has never been a standard approach to systematically design it! Thousands of papers, lectures, tutorials, can be found online about the design process, and everyone is proposing a different approach. The ML/AI guys recently kicked in and started to propose even more approaches based on big buzzwords like reinforcement learning and graph neural networks! On the other hand, some designers just get frustrated with all these fancy methodologies, and just get the job done by some intuition and SPICE-monkeying. So what this live lecture is all about? It is the final verdict! We will start with the basics and end up with how to design a Miller op-amp in less than two minutes! Sounds fake? Join us to see it yourself!

Комментарии • 9

  • @karamany9870
    @karamany9870 Год назад +2

    Do you have suggestions for analog IC design books for intermediate students(not first course)?
    Thanks a lot

    • @getusel
      @getusel 9 месяцев назад +1

      I think every analog design engineer starts with Razavi's CMOS Design book.

  • @RitayanMitraggmu
    @RitayanMitraggmu Год назад +1

    In the table @15:41, is wu1 constant for all 4 rows? If not, then which parameter is constant in the table?

    • @MasteringMicroelectronics
      @MasteringMicroelectronics  Год назад +1

      Yes, Avdc, wp1, and wu1 are constant. Only wp2 is changing.

    • @RitayanMitraggmu
      @RitayanMitraggmu Год назад

      Thanks for the reply. Another question, settling time ts∝1/(zeta*wn)∝1/wp2. But it seems the table is not following that. Which formula had been used to calculate ts?

    • @MasteringMicroelectronics
      @MasteringMicroelectronics  Год назад

      @@RitayanMitraggmu As shown in the lecture, the actual settling time for 0.5% error is measured from simulations. No approx formulas are used.

  • @ebadurrahmankhan9033
    @ebadurrahmankhan9033 Год назад +1

    But sir don't you think this will effect the intuition of an cmos analog design transistor level engineer? They will just know things, but they will not be able to understand they way you understand things like you see on your eyes.

    • @MasteringMicroelectronics
      @MasteringMicroelectronics  Год назад

      ADT gives a big deal of intuition through several tools such as the interactive sensitivity/impact analysis, the gm/ID tuning, etc.
      So, on the contrary, the intuition that takes 10 years to be achieved, can be achieved in less than one year if you are using ADT.

    • @ebadurrahmankhan9033
      @ebadurrahmankhan9033 Год назад +2

      Sir do you guys offer analog and mix signal IC design course in English for international students? Can you refer me on that?