This channel deserves way more attention! It is so hard to find such valuable and rich information nowadays.. Thank you so much for your work, people like you are a huge gain for the community! ❤
Thanks, but you know, I don't really care about subscriptions/views, If I have time to make some interesting experiment, I like sharing. All the information here are pieceful information, useful, but not systematically. Only for those engineers with the same mind set! And also a good way to spot my own mistakes, as lots of people point out my mistakes as well.
A very interesting experiment and one that is in agreement with my personal experience as well. I have found that the difference between using a four layer board with two internal ground planes and a two layer board is very significant when it comes to emissions - after that, subsequent improvements are marginal. However, one reason to use copper ground on the top in a switching regulator layout is for thermal purposes, especially if the MOSFETs are integrated into the controller - I don't think this really needs to extend to the whole of the top layer though.
I think the better reference video to add is this one ruclips.net/video/lBHJ3QamqiA/видео.html (fairly close to what you have in terms of eval board) where they do show that as soon as you screw something else on the board, the ground cut is useless. Further, did no-one check that their symmetrical layout is based on the assumption that they had 2 ground pins? They seriously assume that everyone will connect the PHASE digital input to ground to get "symmetrical layout", and if you don't, well too bad. They literally made a bad layout for either a product that has 2 ground pins, or for marketing. And in my experience, crappy power inductors will be crappy and not contain fields properly, and good inductors will do, so if you are placing capacitors close to the inductor to "shield" fields, you are already grasping at straws.
you only performed a conductive emissions test which determines if you have any common mode radiation coming in/out of your cables. Also, given that the CM filter did not help means it was poorly specified for the load which makes sense because when you design a CLC + Cd pi filter with damping bulk cap you need to know your load cases. separating grounds is a problem concerning return current paths. the flux coming out of the inductor will hit the top ground plane island and induce eddy currents in the copper layers. the island is to reduce the influence of this effect on neighboring components. the shielding capacitors also help with radiation leakage from the inductor. this test would be more conclusive if you performed a localized radiated emission test using RF probes at various points on the board surface to show how the emission pattern differs between designs.
Absolutely, you sound almost like the MPS field engineers in their presentations. I did also try to measure the field using a TEM cell, and the findings are the same. Common mode current on the wirings show the same, which is not surprising because of what is shown on the conducted emission results. It is only a shame that i don't own a chamber, but you know what, I have some lab freiends, who may want to lend me their lab for half a day (maybe in Christmas), and I will do the far field test!
This channel deserves way more attention! It is so hard to find such valuable and rich information nowadays.. Thank you so much for your work, people like you are a huge gain for the community! ❤
Thanks, but you know, I don't really care about subscriptions/views, If I have time to make some interesting experiment, I like sharing. All the information here are pieceful information, useful, but not systematically. Only for those engineers with the same mind set! And also a good way to spot my own mistakes, as lots of people point out my mistakes as well.
This was the type of video, electronic engineers want!
really good examples for conducted emission. i always have similar view about ground saparation. thank you for experiment!
great video! continue your work!
A very interesting experiment and one that is in agreement with my personal experience as well. I have found that the difference between using a four layer board with two internal ground planes and a two layer board is very significant when it comes to emissions - after that, subsequent improvements are marginal. However, one reason to use copper ground on the top in a switching regulator layout is for thermal purposes, especially if the MOSFETs are integrated into the controller - I don't think this really needs to extend to the whole of the top layer though.
Glad to see your experience aligns with this!
I think the better reference video to add is this one ruclips.net/video/lBHJ3QamqiA/видео.html (fairly close to what you have in terms of eval board) where they do show that as soon as you screw something else on the board, the ground cut is useless. Further, did no-one check that their symmetrical layout is based on the assumption that they had 2 ground pins? They seriously assume that everyone will connect the PHASE digital input to ground to get "symmetrical layout", and if you don't, well too bad. They literally made a bad layout for either a product that has 2 ground pins, or for marketing. And in my experience, crappy power inductors will be crappy and not contain fields properly, and good inductors will do, so if you are placing capacitors close to the inductor to "shield" fields, you are already grasping at straws.
Hi Min when your SMPS EMC course is coming?
I will start next week, my friend!
@@MachOneDesignEMC Thanks
you only performed a conductive emissions test which determines if you have any common mode radiation coming in/out of your cables. Also, given that the CM filter did not help means it was poorly specified for the load which makes sense because when you design a CLC + Cd pi filter with damping bulk cap you need to know your load cases. separating grounds is a problem concerning return current paths. the flux coming out of the inductor will hit the top ground plane island and induce eddy currents in the copper layers. the island is to reduce the influence of this effect on neighboring components. the shielding capacitors also help with radiation leakage from the inductor. this test would be more conclusive if you performed a localized radiated emission test using RF probes at various points on the board surface to show how the emission pattern differs between designs.
Absolutely, you sound almost like the MPS field engineers in their presentations. I did also try to measure the field using a TEM cell, and the findings are the same. Common mode current on the wirings show the same, which is not surprising because of what is shown on the conducted emission results. It is only a shame that i don't own a chamber, but you know what, I have some lab freiends, who may want to lend me their lab for half a day (maybe in Christmas), and I will do the far field test!