Digital-on-top Physical Verification (Fullchip LVS/DRC) - Part 3

[@rbalakrishnareddy5076]

Hi Adi Teman,
How to convert gate level netlist to spice level netlist in cadence tool.

[@AdiTeman]

In the video series, I used the Mentor Graphics v2lvs tool (part of the Calibre package).
The tool that is included in the Cadence PVS package is called "v2cdl"
v2CDL [-o CDL_output_file]
Other than that, it works pretty much the same. You will need to refer to the documentation to find out what all the options are.

[@jagadeeswariy8050]

Can we run v2lvs which creates flat cdl from hierarchical netlist?

[@AdiTeman]

Unfortunately, I think the answer is no. From the Calibre User Manual: "Multiple Verilog design files or Verilog library files must be concatenated prior to running V2LVS."

[@jagadeeswariy8050]

@@AdiTeman thanks

[@sadiqbayramov1187]

@@AdiTeman xxg