How to find Gain of Feedback Amplifier Example with JFET & BJT Transistors
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- Опубликовано: 15 окт 2024
- Analysis and How to find AC gain of a Voltage Feedback Amplifier designed with JFET and BJT transistors in three stages are discussed in this circuit video tutorial and example. How to find the open-loop and closed loop voltage gains for feedback amplifier? For more Analog Circuit including Op Amp examples please see • Electrical Engineering...
The N-channel Junction JFET Junction Field Effect Transistor is DC biased properly with zero DC voltage at its gate resulting in a negative DC gate-source voltage with a transconductance gain of gm = 3 milli Siemens in this example. For both PNP and NPN Bipolar Junction Transistors a current gain Beta = hfe = 100 is assumed with intrinsic base-emitter resistor (hie) of 2 kilo ohm as seen from the base of BJT transistors. The PNP-NPN transistors are configured in a semi Sziklai Darlington style pair to boost AC current. The feedback loop is analyzed and shown to be a negative voltage feedback loop that counteracts the impact of input small signal on the gate-source voltage of the JFET transistor. The equation of closed-loop gain is equal to open-loop gain divided by the one plus loop gain is reviewed as well in this example. A combination of circuit laws including voltage division, current division along with JFET transconductance and current gain of BJT transistors are applied to find the open loop and closed loop voltage gains.
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I hope these Circuit design and analysis videos are helpful.
That was beautiful! Thank you for that analysis. I learned something new today.😁
My pleasure, thanks for watching and comment. Glad that you like this circuit analysis video and it is useful. I will post more feedback amplifier examples. 🙏🙋♂️
Really appreciate it
You're welcome. Thank you for watching and for comment. Glad that you liked this Feedback Amplifier Circuit video. For more Amplifier, BJT, JFET Circuit examples please see:
Sawtooth Oscillator with Op Amp, JFET and BJT Transistors ruclips.net/video/5zHXTx-Vl20/видео.html
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Push-Pull Power Amplifier with Darlington Transistors ruclips.net/video/866MYibo8yE/видео.html
Analog Computer to Raise Signal to power n ruclips.net/video/IUTlBH1UraE/видео.html
For more analog signal processing examples see: ruclips.net/p/PLrwXF7N522y4c7c-8KBjrwd7IyaZfWxyt
I hope you also enjoy these circuit analysis videos. Thanks again. 🙏
DC coupled circuits like this usually need a few times stepping back and forth. Total DC current gain (300 ohms current/ Id ) is more than 1000 (as you calculated correctly). Starting with Id of almost 5 mA, means BJTs will get into saturation and we can not continue calculating the way you did. The other point is in the feedback loop we can not ignore the Source impedance (which is 1/gm). Either we should reduce the JFET operating point current(Id) drastically, or change other parameters to get back into linear operating mode of the circuit.
Thanks Dariush for watching and for sharing your thoughts, feedback and suggestions. I appreciate your detailed attention. Proper DC bias is fundamentally important in setting up amplifiers as you also pointed out. In this circuit, I have not specified what DC voltage is applied and hence DC current of JFET is not specified to be 5 mA. The Id-Vds curve that was presented was for illustration purposes and to just illustrate and visualize the meaning of transconductance of the JFET transistor. It is not trying to state that the DC current of JFET is 5mA in this circuit. As for the 1/gm, this is a parallel to series voltage feedback network that is modeled by a hybrid two-port network. Hence, the feedback factor Beta in the hybrid two port is therefore computed as Beta=V1/V2 assuming we cut the wire connecting the 0.5kohm resistor to JFET source (hence no need to consider 1/gm in computing beta in this model). That leaves a voltage division between 0.5K and 25K to compute beta of the feedback. I hope this is helpful. Thank you again.🙏
It is better to to do a complete DC analysis of the circuit, before starting any AC analysis, since AC parameters depend strongly on the DC operating point of each transistor.
Thanks again Dariush for watching and your comments. I agree, there is just a concern that how much content I can put in one video. But, sure, I will post another Feedback Amplifier example soon starting from DC analysis. Thanks again for your suggestion.
There is one more step, that you can do to demonstrate what's happening when you have open loop with large gain. Divide the result with Avo. You will get 1/(beta + 1/Avo). From there, it's clear that if your Avo is large enough, you can discard whole 1/Avo and Avf ≈ 1/beta.
Thanks for watching and your good practical approximation. Just a minor note that to use it with negligible error, rule of thumb is the total loop gain of circuit beta*Avopen >> 1 which in this case is not since beta*Avopen =8. Therefore the 12.6% error between actual closed loop gain of 45.3 and approximation of 1/beta=51 is not negligible. Nonetheless your practical suggestion is useful as a quick first round holistic view of what range of gain a designer can expect from the closed loop amplifier. For more analog circuit examples and Videos please see ruclips.net/p/PLrwXF7N522y4c7c-8KBjrwd7IyaZfWxyt
Thanks again 🙋♂️
@@STEMprof Yes, I use the Avo>>beta^-1 rule of thumb (which is the same equation just written differently). It's also good to note that what is and what isn't negligible is relative to the application. There are some for which 12% error is fine, in some other even 0.1% can be a problem.
In practical electronics, we often work the other way around. Measure the frequency response of the open loop gain and then select the required beta for the feedback.
I think that last time I've actually calculated it by hand was back at school. But that's why I like videos like this, even if I know the subject, it's good to refresh it from time to time. So thank you.
@@mrkv4k You are very welcome. Glad that you liked this voltage feedback amplifier circuit video and Happy that it is useful. I will post more feedback examples. Thank you again for watching and your comments. For more Circuit and Op Amp examples please see ruclips.net/p/PLrwXF7N522y4c7c-8KBjrwd7IyaZfWxyt
Thanks again 🙋♂️
You can't just pick hie (or rbe) as 2K and pretend the three transistors are operating in their linear region. It depends too strongly on the collector current of T2 because rbe = 26mV/Ic at room temperature. So an rbe of 2K would imply a collector current of 13μA, giving just 5K x 13μA = 65mV at the base of T3, which would be off.
Do the open-loop voltage gain analysis by calculating voltage gain, stage by stage. For an FET in common source mode, the voltage gain in its linear region is Rd/(Rs+1/gm); in this case Rd is actually the parallel combination of 10K and β x rbe of T2. If the transistors are all biased accurately for dc, and assuming a supply voltage of around 15V, we would expect T2's collector to be at about 8V. That means its collector current is 8V/5K = 1.6mA, making its rbe about 26mV/1.6mA = 16Ω. With a β=100, that makes the resistance looking into the base of T2 = 1.6K, dominating the 10K drain resistor for an effective drain resistance of 1.4K. So the voltage gain of the first stage would be 1.4K/(0.5K + 0.33K) assuming gm=3mS. First stage gain = 1.7.
For a BJT in common emitter mode such as T2, the voltage gain in its linear region is Rc/(rbe + Re). We already know that T2's rbe is about 16Ω, and it has no emitter resistor (i.e. Re=0). Since T3 is in in emitter follower mode, its voltage gain is 1, but its input impedance is β(rbe + Re). Assuming again the output is around half of the 15V supply, T3 will be passing about 25mA, making its rbe about 1Ω. So T3's input impedance may be taken to be 100 x (0.3K + 1) = 30K, making the effective load on T2 equal to 5K and 30K in parallel, which is 4.3K. The voltage gain of the second stage is therefore 4.3K/(16Ω+0) = 270.
Since the voltage gain of T3 is very close to 1, the open loop gain of the three stages is 1.7 x 270 = 460.
Your calculations are not too far off, but your mistake is to assume that gm is fixed for a BJT, which it most definitely is not. As you can see from my calculations, 1/gm for T2 is 16Ω, not 2K, and 1/gm for T3 is 1Ω, not 2K. Have a good read through my calculations and decide for yourself if it doesn't represent a simpler and more accurate way of calculating the gain.
Thanks for watching and for sharing your feedback and suggestions. I appreciate your detailed attention and your good points. For a more comprehensive Feedback Amplifier Analysis please see ruclips.net/video/6dLMxpLNKv4/видео.html that goes through all details including DC analysis, hie calculations and then AC analysis. I am aware that Proper DC bias (defining hie of BJT) is fundamentally important in setting up amplifiers as you also pointed out. In this video, I wanted to focus on AC analysis by assuming that hie of BJT transistors are already computed. I agree that it'd have been better if I would have precalculated the DC bias and hie values beforehand and use the actual hie values instead of hie assumption (to just focus on AC analysis). I hope this clarification is helpful. Thank you again for watching and your comment. 🙏
@@STEMprof Thanks for your response. It does show that designing the collector currents of each BJT stage to ensure linear operation is an important first step in any multistage amplifier design. If you know that the second stage is going to draw about 2mA and the emitter follower output is going to draw 25mA, then you have the necessary first steps in characterising the amplifier.
@@RexxSchneider You're welcome. Thanks again for your interest in these circuits and for sharing your insights and feedback. I am thankful 🙏 . I will post more feedback amplifier examples soon in my Analog Circuit Playlist ruclips.net/p/PLrwXF7N522y4c7c-8KBjrwd7IyaZfWxyt . I hope you find them interesting as well. Happy Holidays! 🙂