AI/ML Accelerator Verification Tutorial High-Level Verification of C-level design

Presented at DVCon Europe 2021
Session T2.3
Introduction - One of the fastest growing areas of hardware and software design is Artificial Intelligence/Machine Learning (AI/ML), fueled by the demand for more autonomous systems such as computer vision (CV) for self-driving vehicles, voice recognition for personal assistants and many others. Many of these algorithms rely on Convolutional Neural Networks (CNNs) to implement deep learning systems. While the concept of convolution is relatively straightforward, the application of CNNs to the ML domain has yielded dozens of different neural network architectures. While these networks can be executed in software on CPUs/GPUs, the energy consumption of these software-based solutions make them impractical for most inferencing applications, the majority of which involve portable, low-power, edge computing devices.
Thus, the emergence of customized AI/ML hardware accelerators to meet the numerous, stringent, and potentially conflicting requirements. High-Level Synthesis (HLS) can provide the needed flexibility and abstraction to efficiently and quickly realize these designs in RTL. However, when working with HLS at the C-level, many have questions about what does verification look like? Waiting to verify until you have post-HLS RTL is too late and too inefficient. This workshop demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques.
Summary - Many newcomers to HLS have questions about how to take advantage of the dramatic productivity benefits of raising the design and verification abstraction but still have the confidence that they have with their verification current methodology.
This technical workshop, intended for design and/or verification teams, will demonstrate how a High-Level Verification (HLV) flow built around HLS and C-level design can dramatically speed up verification compared to a traditional RTL based flow. It will use an AI/ML hardware accelerator design example, written in C++ and using the open-source MatchLib SystemC library originally developed by NVIDIA, to step through the verification methodology and tools. This example will be provided as open source at the conclusion of the workshop.
The workshop is a verification case study of the AI/ML accelerator design in an AMBA AXI4 subsystem. It will demonstrate how the pre-HLS simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found until very late in a hand-coded RTL design methodology. Comprehensive verification on the pre-HLS design will be demonstrated highlighting both tools and flows(coverage, assertions, formal techniques, etc) gleaned from known and trusted RTL verification methodologies, as well as how the same environment can be reused post-HLS to quickly close coverage on the resulting RTL.
Presenters:
David Aerne & Jonathan Craft - Siemens
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