CMOS inverter example | critical voltages | Noise margin

[@GayatriLondhe]

You have solved this problem correctly explaination is also good but the video quality is too bad... Please improve it so it is more understandable

[@rutweakchacha1558]

Do we have to calculate 2 Vout eqns ?? Different for Vil andVih

[@Heisenberg-pr1hk]

It always the low quality video

[@rishabhmishra2266]

How did you solve that last equation when you are multiplying 2 brackets and suddenly enter you +10.89 i know it uper there but you directly taken this where that -6.62vout+21.846 of the equation?????
Bro reply fast bohot der se dimag khaa raha hai ye

[@siddharthgholap9092]

Nyce

[@gokayakbas6350]

Bro do you know how we find Vtp and Vtn ?

[@pranavterkhedkar2831]

Script hai bhai k paas 😅

[@srikanth43354]

How did you said pmos in linear and nmos in saturation

[@AKLESHKUMAR-dr3vm]

to calculate VIL in cmos .

[@arqamkhan8230]

dude my exam is tomorrow, reply as fast as u an
how did u get equation 'one' in the first place. Second , how would u calculate all these values for general cmos circuit. I want to know specifically how did u calculate 'V input for low'. help me

[@rutweakchacha1558]

For Vil , he took the first Vout value and put it in eqn of Vil in terms of Vout. How was the exam btw

[@RiddhiChandorkar1510]

Thank you so much sir

[@malharnavle5051]

vIL kase aya ??

[@oosanam]

thanks bro