DVD - Lecture 11b: Additional issues in Sign-off Timing

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 11 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 11 wraps up the RTL to GDS flow with the extra steps that are needed to take a design that has finished place and route and prepare it for tape-out.
Lecture 11b continues the discussion of signoff timing with Path-based analysis (PBA) and RC extraction corners and then continuing to the presentation of a general signoff flow towards tape-out.
Lecture slides can be found on the EnICS Labs web site at:
enicslabs.com/...
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Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University