Hi Shetty, Many viewers have asked same question and I was thinking the best way to explain it. When an input is floating, its voltage level is unpredictable , It could be either 0 or 1 or somewhere in between 0 to 1. If its value is in 0 or 1 , its very good as one of the transistor of CMOS pair is in OFF state, so there is no power loss. But question is, will it remain fixed in one state?? We can't say yes, as there are many factors which may change its state as floating input is very prone to affect by noise. So If unnecessary an input will toggle of vary , it will consume power. Other case could be, suppose the input is at neither 0 nor at 1 as it is unpredictable and it lies in between threshold voltage of nMOS and pMOS, This will be very dangerous, as it will provide a direct current path (will cause short circuit current - Isc) from VDD to GND for an unknown duration. So If we do not tie the input of a CMOS Design, We can not be sure that above situation will not occur which will lead lots of power loss and heating up the circuit. So its always a best practice to tie the input either 0 or 1. so we are sure in any case one of transistor is always in OFF state and there are no power loss. Hope you understand it clearly.
Well done - thank you for the overview of spare cells. I am working through a first Innovus design and was adding spare cells and found your video helpful in what I was doing.
Very good explanation !! Totally convinced I am seeing few statements like leakage power dissipation increase and area increase etc.. I have a suggestion if you like to accept it . Whenever concepts like power, capacitance , current and any other parameters comes into existence with the current topics ,the immediate question raises to everyone including me is "WHY?" For eg :- leakage power dissipation increases . I am interested to know why and how . Having small equations might actually support the understanding much better with proof . Have a great day ! Thank you :-)
Spare cells can't be used as filler cells because 1. It will consume more area and power 2. Spare cells are not available in all size But vice versa can be possible we can use filler in place of spare with appropriate logic.
I've ever heard that eco filler can be added for post-mask ECO to replace spare-cell. I searched some materials but not understood well. Can you help explain how eco filler works and the differences between these two choices? If you can make a video, I think it will help us a lot.
Filler cells are just the cells to make the Nwell continuity and doesnot have functionality of these cells. Spare cells are the gates which contain functionality of cells which are used in design for eco.
spare cells can be used as filler cells but the problem is after manufacturing the chip many spare cells can be used for the design change. So because we used many spare cells then no many filler cells are there in the design to nwell and psub continuity so there is a possibility of many DRC's.
Right !! But explanation is not appropriate 1. Spare cell are also a normal standard cell, so there is no issue with well continuity. These cells will also provide the well continuity. But problem is only of size, we have filler cells with large variety of size so we can cover all small or big gaps but in spare cells we don't have such variations of size. so we can not fill all gaps. 2. Spare cell will cause increase much static power consumption compare to filler cells.
@@TeamVLSI I would like to add one more thing along with this... I have seen few standard cells using layer M2 inside. If we fill with spare cells, if any cell added to spare pack having M2 inside will create shorts, and mess up everything.
Hi Sir, I am a BTech graduate.I want to start my career in VLSI Analog Layout. Please start the videos from scratch.So that freshers can get job very easily. If possible please explain below topics through cadence virtuoso. Introduction to cmos Fabrication steps wafer Formation Photolithography. Typical cmos inverter fabrication steps. Typical cmos inverter fabrication steps. Dual pattern lithography, Finfet fabrication steps Introduction-Aspect of VLSI design- IC MASK design Introduction to full custom Introduction to Semicustom design flow Foudation Ips Introduction to CMOS Layouts Design Rule and how to read DRM Design of basic gates Layout Design of NAND4x4 cell, Concept of half design rule LVS/DRC concept Interconnects, Sheet resistance, RC delay Crosstalk, latch up effect, STI stress effects, WPE effects, Antenna effect Electromigration, Irdrop Parasitic extraction and delay estimations Introduction basic buidling blocks of SOC- IPS Standard cell Layouts- Architecture, Std cell tracks concepts, Abutment and Half rule Memory Layout desing-Architecture, Muxing concepts, Leafcell concepts, Abutment and verication techniques, compiler flow introdution Analog Layouts - Concept of matched layout - ESD issues Integer N PLL DAC Thankyou .
Hi dear I would suggest you start learning from text book first. In video lectures we try to cover only important concepts and tool flow, these lengthy theoretical part is not possible to cover.
@@TeamVLSI Yes sir they will maintain well continuity.But if we use them as fillers there is a chance of misfunctionality because of cross talk as they are nothing but std cells. But fillers don't have any functionality
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I have doubt sir, y we can't keep the inputs of spare cells unconnected or floating?
Hi Shetty,
Many viewers have asked same question and I was thinking the best way to explain it.
When an input is floating, its voltage level is unpredictable , It could be either 0 or 1 or somewhere in between 0 to 1. If its value is in 0 or 1 , its very good as one of the transistor of CMOS pair is in OFF state, so there is no power loss. But question is, will it remain fixed in one state?? We can't say yes, as there are many factors which may change its state as floating input is very prone to affect by noise. So If unnecessary an input will toggle of vary , it will consume power.
Other case could be, suppose the input is at neither 0 nor at 1 as it is unpredictable and it lies in between threshold voltage of nMOS and pMOS, This will be very dangerous, as it will provide a direct current path (will cause short circuit current - Isc) from VDD to GND for an unknown duration.
So If we do not tie the input of a CMOS Design, We can not be sure that above situation will not occur which will lead lots of power loss and heating up the circuit.
So its always a best practice to tie the input either 0 or 1. so we are sure in any case one of transistor is always in OFF state and there are no power loss.
Hope you understand it clearly.
Got it sir😇...thank you🙌
@@TeamVLSI superb explanation
@@TeamVLSI 🙏
Well done - thank you for the overview of spare cells. I am working through a first Innovus design and was adding spare cells and found your video helpful in what I was doing.
Thanks Patina,
Glad it was helpful!
Very good explanation !!
Totally convinced
I am seeing few statements like leakage power dissipation increase and area increase etc..
I have a suggestion if you like to accept it .
Whenever concepts like power, capacitance , current and any other parameters comes into existence with the current topics ,the immediate question raises to everyone including me is "WHY?"
For eg :- leakage power dissipation increases . I am interested to know why and how .
Having small equations might actually support the understanding much better with proof .
Have a great day !
Thank you :-)
Thanks Vicky,
Really nice suggestions and totally acceptable. I will keep in mind the point you suggested.
Keep connected and keep learning...
Spare cells can't be used as filler cells because
1. It will consume more area and power
2. Spare cells are not available in all size
But vice versa can be possible we can use filler in place of spare with appropriate logic.
Rightly said @parth
I've ever heard that eco filler can be added for post-mask ECO to replace spare-cell. I searched some materials but not understood well. Can you help explain how eco filler works and the differences between these two choices? If you can make a video, I think it will help us a lot.
Ok, We will try to do that.
Filler cells are just the cells to make the Nwell continuity and doesnot have functionality of these cells.
Spare cells are the gates which contain functionality of cells which are used in design for eco.
Hi Aneela,
My question was, can we use spare cells in place of filler cells?
No
I have a doubt regarding with the placement of spare cell. Where we place the spare cells? At regular intervals ? and at what stage ?
Hi Ashmeet,
We sprinkle the spare cell through out the design before placing the standard cells.
spare cells can be used as filler cells but the problem is after manufacturing the chip many spare cells can be used for the design change. So because we used many spare cells then no many filler cells are there in the design to nwell and psub continuity so there is a possibility of many DRC's.
Hi VBR,
I expect answer YES or NO first, then explanation. You have explained well but it mixed up with yes and no...
Answer is no
We can't use spare cells as filler cells because of above said reason
Right !!
But explanation is not appropriate
1. Spare cell are also a normal standard cell, so there is no issue with well continuity. These cells will also provide the well continuity. But problem is only of size, we have filler cells with large variety of size so we can cover all small or big gaps but in spare cells we don't have such variations of size. so we can not fill all gaps.
2. Spare cell will cause increase much static power consumption compare to filler cells.
@@TeamVLSI Thank you
@@TeamVLSI I would like to add one more thing along with this...
I have seen few standard cells using layer M2 inside.
If we fill with spare cells, if any cell added to spare pack having M2 inside will create shorts, and mess up everything.
what is the problem of making inputs floating in layout?
Hi VBR,
I have answered this question in @Shetty Praneeth comment.
Hi Sir,
I am a BTech graduate.I want to start my career in VLSI Analog Layout. Please start the videos from scratch.So that freshers can get job very easily.
If possible please explain below topics through cadence virtuoso.
Introduction to cmos Fabrication steps wafer Formation Photolithography.
Typical cmos inverter fabrication steps.
Typical cmos inverter fabrication steps.
Dual pattern lithography, Finfet fabrication steps
Introduction-Aspect of VLSI design- IC MASK design
Introduction to full custom
Introduction to Semicustom design flow
Foudation Ips
Introduction to CMOS Layouts
Design Rule and how to read DRM
Design of basic gates Layout
Design of NAND4x4 cell, Concept of half design rule
LVS/DRC concept
Interconnects, Sheet resistance, RC delay
Crosstalk, latch up effect, STI stress effects, WPE effects, Antenna effect
Electromigration, Irdrop
Parasitic extraction and delay estimations
Introduction basic buidling blocks of SOC- IPS
Standard cell Layouts- Architecture, Std cell tracks concepts, Abutment and Half rule
Memory Layout desing-Architecture, Muxing concepts, Leafcell concepts, Abutment and verication techniques, compiler flow introdution
Analog Layouts - Concept of matched layout - ESD issues
Integer N PLL
DAC
Thankyou .
Hi dear
I would suggest you start learning from text book first. In video lectures we try to cover only important concepts and tool flow, these lengthy theoretical part is not possible to cover.
No we cannot use spare cells as fillers. Fillers are used to maintain NWELL continuity. And these spare cells will not maintain NWELL continuity.
Why can't provide well continuity by spare cells? These cells are the same cells which we are using for other logic implementation.
@@TeamVLSI
Yes sir they will maintain well continuity.But if we use them as fillers there is a chance of misfunctionality because of cross talk as they are nothing but std cells. But fillers don't have any functionality
Hi.. What happens if inputs are kept floating?
Hi Pavan,
I have answered this question in @Shetty Praneeth comment. kindly see there.