Maybe a dumb question, but if the gate completely surrounds the "wire", where do the charge carriers go when the field is applied, and where is the depletion zone? Is it like a skin effect where the holes are pushed into the middle of the wire and conduction happens on the edges?
@@cacssarcaeustan2543It doesn’t. It is one transistor. Think of the stack of 3 ribbons as an alternative way to create a single channel. Back when transistors were simpler and planar, the 3 ribbons together would have been as wide as a single channel where all 3 ribbons were in the same plane and abutting each other; a single, 3x as wide, channel. But with the 3 ribbons, each 1/3 of the formerly wider and simpler channel is now controlled by the gate from all sides, providing greater control. And in a smaller area. Remember that a planar transistor’s W/L ratio determines its strength, and L is minimized. So making a stronger transistor would mean making it wider. Instead of making a single channel wider, three channels are stacked on top of each other. That’s my take.
What I don’t get is that the 3 stacked channels imply that silicon is deposited at the core of those ribbons, instead of just having a simpler planar silicon wafer that gets doped in the N and P regions way back when. Isn’t depositing silicon like this quite different than growing a silicon ingot with a mono crystalline crystal structure? I think I’m missing something because what seems like a big difference is never discussed, that I hear.
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Very informative, thanks for sharing. The complexity of GAA structure is formidable I would say.
Excellent lecture on the GAA structure and associated process and metrology challenges
Maybe a dumb question, but if the gate completely surrounds the "wire", where do the charge carriers go when the field is applied, and where is the depletion zone? Is it like a skin effect where the holes are pushed into the middle of the wire and conduction happens on the edges?
Yeah thats a good question, maybe the charge carriers come will flow from the source and drain once the gate is properly biased?
Yes and also how does a single gate control different channels independently?
@@levarg91492 all three at once? so one gate runs three channels at once, the same, for the example shown on this video's white board.
@@cacssarcaeustan2543It doesn’t. It is one transistor. Think of the stack of 3 ribbons as an alternative way to create a single channel. Back when transistors were simpler and planar, the 3 ribbons together would have been as wide as a single channel where all 3 ribbons were in the same plane and abutting each other; a single, 3x as wide, channel. But with the 3 ribbons, each 1/3 of the formerly wider and simpler channel is now controlled by the gate from all sides, providing greater control. And in a smaller area.
Remember that a planar transistor’s W/L ratio determines its strength, and L is minimized. So making a stronger transistor would mean making it wider. Instead of making a single channel wider, three channels are stacked on top of each other.
That’s my take.
What I don’t get is that the 3 stacked channels imply that silicon is deposited at the core of those ribbons, instead of just having a simpler planar silicon wafer that gets doped in the N and P regions way back when. Isn’t depositing silicon like this quite different than growing a silicon ingot with a mono crystalline crystal structure? I think I’m missing something because what seems like a big difference is never discussed, that I hear.
Good sharing.
Thanks for visiting