I recommend using both CO and CS together. For instance, you could set CO to -15 and CS to -5 or -10 depending on the frequency. However, keep the scalar within a 4X range, as 10X would significantly increase voltage and heat dissipation, resulting in negative returns for most users.
The process will be the same but the results may vary. You can check my longer video for more details on the process ruclips.net/video/tEJiQcPA4p0/видео.html
Fanboys will sugar coat amd but not one will tell you about the second recycled garbo ccd on the new flagship chips... nobody will complain if they were within 100mhz of each other, but it seems to be a fact that the difference is a constant 300mhz in all 9950x's.
Differently binned chiplets keep the price down and probably maximize profits too. But if you paid attention to the video it seems it's possible to get CCD1 within 100 MHz of CCD0 with a simple overclock. I'm sure with a little extra effort you could match them both. This is also why the consumer can have 16 real cores on a CPU package for a reasonable price.
@@maxwellsmart3156 It's not even 16 core it's 2x8 like zen2 is not 8 core but 2x4 if you have latency sensitive tasks half of a CPU is useless ngl go play cinebench with your "16" core
@@fefsefefesfsefsef2733 Zen3, Zen4 & Zen5 the CCX=CCD=8 cores. Inter CCD latency only matters when the idiot Windows scheduler moves a thread from one CCD to another when that thread has data pointers left in the L3 cache on the other CCD. Do I care that 2 chiplets are used and that frequency is asymmetric, no, no I don't, because it just doesn't matter when the value is apparent.
@@maxwellsmart3156 They can't even bin fucking CPUs my friend has 7500f and his ram goes 6400mhz 1:1 with 1.28v soc my 7800x3d needs 1.24v for 6000mhz AMD CPUs are a joke at least intel can bin their CPUs properly
I recommend using both CO and CS together. For instance, you could set CO to -15 and CS to -5 or -10 depending on the frequency. However, keep the scalar within a 4X range, as 10X would significantly increase voltage and heat dissipation, resulting in negative returns for most users.
Super useful reference. Thank you so much.
nice video!! I'm hoping if you can cover how the curve shaper practically used on top of it, as you covered that topic few months ago
I cover the OC stategies for the 9950X in more detail in the full length guide ruclips.net/video/tEJiQcPA4p0/видео.html
man this was quite the "did I get moved to a different universe" until I realized there was no x35 at the end of the name. what a mindfuck that was
Can you do a video on overclocking a 12900k with asus AI tweaker bios
does this work with the 9900x specifically?
The process will be the same but the results may vary. You can check my longer video for more details on the process ruclips.net/video/tEJiQcPA4p0/видео.html
Hey guys is it possible to delid the 9950x?
yes like every cpu
Wath we can do to reduce the ddr5 6400 latency?
I use a 9700x with ddr5 6400 i try a lot but i can not obtain better latency that 67😢
Have you already try set tREFI to 65535?
Buildzoid (Actually Hardcore Overclocking) should have pretty complete guide how to set memory timings for maximum memory performance.
Fanboys will sugar coat amd but not one will tell you about the second recycled garbo ccd on the new flagship chips... nobody will complain if they were within 100mhz of each other, but it seems to be a fact that the difference is a constant 300mhz in all 9950x's.
Dual ccd is a scam, always has been
Differently binned chiplets keep the price down and probably maximize profits too. But if you paid attention to the video it seems it's possible to get CCD1 within 100 MHz of CCD0 with a simple overclock. I'm sure with a little extra effort you could match them both. This is also why the consumer can have 16 real cores on a CPU package for a reasonable price.
@@maxwellsmart3156 It's not even 16 core it's 2x8 like zen2 is not 8 core but 2x4 if you have latency sensitive tasks half of a CPU is useless ngl go play cinebench with your "16" core
@@fefsefefesfsefsef2733 Zen3, Zen4 & Zen5 the CCX=CCD=8 cores. Inter CCD latency only matters when the idiot Windows scheduler moves a thread from one CCD to another when that thread has data pointers left in the L3 cache on the other CCD. Do I care that 2 chiplets are used and that frequency is asymmetric, no, no I don't, because it just doesn't matter when the value is apparent.
@@maxwellsmart3156 They can't even bin fucking CPUs my friend has 7500f and his ram goes 6400mhz 1:1 with 1.28v soc my 7800x3d needs 1.24v for 6000mhz AMD CPUs are a joke at least intel can bin their CPUs properly