For FF1 to FF2 there are two inverters in clock path effectively if we don't consider the common inverter delay between FF1 and FF2. So, now two inverter delays are giving negative skew which is fine. But what about clock jitter madam, I'm confused like do we have to consider only -2*(jitter) always irrespective of the number of inverters in clock path? Tclk+tskew-2*(jitter) is what the original equation on right hand side for setup analysis. But will that -2*(jitter) term changes if there are multiple delays, let's say inverter and buffer is also there with each having same plus or minus 10% delay variation. Then will the equation holds same or it will change?
Thanks for the question! The terms tj1 and tj2 in the generic equation which given in slide 2 refers to the amount of random deviation of each clock edge. Whenever the inverter delay is given skew and jitter depends on no. of inverters but when jitter is mentioned in the question then it would be -2*(jitter)
For FF1 to FF2 there are two inverters in clock path effectively if we don't consider the common inverter delay between FF1 and FF2. So, now two inverter delays are giving negative skew which is fine. But what about clock jitter madam, I'm confused like do we have to consider only -2*(jitter) always irrespective of the number of inverters in clock path? Tclk+tskew-2*(jitter) is what the original equation on right hand side for setup analysis. But will that -2*(jitter) term changes if there are multiple delays, let's say inverter and buffer is also there with each having same plus or minus 10% delay variation. Then will the equation holds same or it will change?
Thanks for the question! The terms tj1 and tj2 in the generic equation which given in slide 2 refers to the amount of random deviation of each clock edge. Whenever the inverter delay is given skew and jitter depends on no. of inverters but when jitter is mentioned in the question then it would be -2*(jitter)