It still blows my mind that we're in the billions of transistors on CPUs now, basically every single one has to work or the whole chip is useless, and these things run for *decades*. I don't know of any other thing we make as a species that's good for quadrillions of operations with zero maintenance.
Just keep in mind that these situations are being designed by individuals and then being taken and tweaked for scalability by others. Cooperation is the real magic of Engineering.
@@Teth47 I would imagine, that with that scale of transistors, and to have a faulty one kill a whole chip, they will build a few redundancies in, so that if a portion of the chip has a fault, they can just fuse it out, and have a backup circuit take up the slack. At least, that's how I would do it, if designing something with that number of potential failure points. I'd build redundancies in so chips could be "saved" even if one critical part had a fault, and a have a fuse map to choose which parts to enable/disable. Sure, it's eats up some silicon space, but if you has even just 1% used for backup circuits, and it could rescue otherwise failed/faulty chips, I think it would be worth it.
For ~40 years,I worked at the IBM foundry where they built/tested semiconductors. (wrote software to run the line) IBM no longer manufactures their own chips...but they still design them and monitor every step of the manufacturing process. It is interesting that most folks dont even think of IBM when "tech companies" are discussed.
I guess them pulling out of selling office/consumer machines to focus on cloud/enterprise hardware and R&D pushed them out of focus for most people...the name is well known, but many people have no idea what they're on about these days because there's little to no (obvious) presence outside of IT space
right, what ever happened to IBM? They used to be THE tech leader, but now who knows IBM? They design chips, they have AI, and they are working on quantum computing. Strange.
@@ketzbook cutting edge tech isnt meant for consumers. microsoft is a consumer based company along with apple/etc... theyre focus is consumer userability not pushing the limits of science.
4:46 - I worked at IBM a few years ago (IBM Software Lab). And I remember quite distinctly that we were strongly encouraged to come up with patent applications for the company. Anything was fine as long as it was patentable. We were rewarded with a salary bonus for a successful patent application.
Lithography. You "print" with an acid resistant and removable material, give it a dunk in acid then remove the printed material. There are more complicated processes. The mechanical tolerances of the "printer" determine how small you can print. The failure rate multiplied by the die size will determine the yield rate because of the two dimensional nature.
There's some promising developments in increasing the length they can grow carbon nanotubes, but we still have a long way to go before we're consistently growing nanotubes of indefinite length.
Moore's law was never about this industry jargon of 7nm and 2nm. Those are not the defining limits to how many transistors can be put put on 1000mm square integrated circuit. We could very well have another 12000 times increase in the number of transistors on chips and that is without the actual chip getting larger. So we may have another 12 to 16 doublings ahead of us in terms of how many transistors can be crammed on to a chip. So your Nanotube revolution maybe at some stage play a part.
Glad to have discovered a channel that actually gets the current state of processors and goes into as much detail as possible. Great and well researched content!
I don't think that removing one bottleneck solve the scaling issue though. The resolution of the lithography process might be high enough to keep increasing the transistor density, but does that mean that it's practical to do so? As far as I understand the real issue might not be Moore's law, but Dennard scaling. If the power density gets to a point where we can't find ways to practically cool a silicon die, we're just hitting a different bottleneck instead.
Thanks for explaining the disconnection from different companies "nanometers" and the real physical dimensions. I think this is what a lot of people don't understand.
I'd care more about the fact Jim Keller used Comic Sans for his presentation if he wasn't talking about such complex things. The absurdity of describing such technology in Comic Sans is actually very fitting
Comic sans is more a cultural backlash from graphist like me due to the democratization of fonts and the loss of power of the expert, it became the symbol typographer rallyed around for it's misused in some context, however that reputation is far fetch and the mockery for using it is a bit overdone, comic sans is basically normal people trying to inject humanity against overly formal font design (which is why the font was created in a first place, because using times new roman in a kids birthday card was equally stupid). Nobody can tell me helvetica is a font designed to be at human scale.
@@NeoShameMan Comic Sans was created as the screen font for Microsoft Bob. It was never intended for regular use. Using it for technical purposes is funny at first but actually distracts from the content. I don’t know what you mean by human scale, but Helvetica is one of the classic typefaces of the 20th century. Love it or hate it, it should not be dismissed. I can highly recommend the “Helvetica” documentary that came out several years ago.
@@germansnowman i know all the historical details of these two fonts, even why p and q are different in comic sans and why the middle bar of the m is crooked, i havw entire book about helvetica and how pauler scher tried so hard to avoid that damn overuse fonts, o know the context, a single god damn documentary won't change my mind 😂 The reputation that comic sans is hard to read is all made up, sans serif font use to be said the same, now they are standard. history is much more nuanced, and contextual cultural aspect add complexity, the but give you the full picture.
@@NeoShameMan Fair enough. I just thought you did not know all that because you said that Comic Sans was made for kindergarten posters. In any case, I did not say Comic Sans is hard to read; my point is that typography should serve the content, and typefaces convey certain moods and connotations. If one knows the rules, it’s OK to break them intentionally. However, I thought that the original Higgs Boson presentation by CERN was very much devalued by its unironic (and very likely uneducated) use of Comic Sans.
Interesting stuff. Didn’t realise how significant EUV has been. Bit of a holy grail it sounds like. I remember reading articles about it being prototyped.
Imagine not only being super smart, but also being so cool you get open invitations to industry leading research facilities, AND having an adorable cat
cats are not adorable they are the worse pet, not loyal, wont help you, wont stand by you, wont protect you, they are a LAZY persons pet as they just go do what they want. not to mention they kill other animals just for sport, you say dogs do? no dogs can be trained to not do or to do anything, cats ingeneral cant be trained to do hardly anything, cat ppl are just the worse
It's nice to know not only what Intel/TSMC/AMD does, but also what is actually researched, great video. Here are my 2 cents for the algorithm, this channel needs to grow.
Keep in mind that the minimum feature size (2nm) is *much* smaller than the actual transistors. At 333M transistors per square mm, the transistor average spacing is 55nm. That is about 260 silicon atom diameters, while 2nm is only 9.5 atomic diameters.
@@TechTechPotato Yes, I just wanted the viewers to realize how misleading the names are. The chart of transistor densities that you showed, does convey the inconsistencies between manufacturers, but not the magnitude of the difference between feature and transistor size. If you read through comments here and elsewhere, you find that many people still think the names are the transistor sizes.
Judging by your comment, it appeared as if you hadn't watched the video. Which is what a lot of people making those sorts of comments you're referring to end up doing as well.
By chance this video was suggested, and as a former semi worker my mind is officially blown. At RCA Findlay (later Harris) we advanced to 0.5 um using i-line Canon FPA 1500 steppers back in the early 1990s; that was a big advance from the MPA-501 that were only 1.5 um line width. Thanks for this video.
The real tech in semiconductors is from ASML though. They made these EUV machines that make the chips, the only one that can. ASML have been the silent driving force behind all the innovation over the last 10 to 20 years. That is the lithography machines that print the designs on the silicon wafer. If you nuke this 1 company and all its people, research. We go back like 10 to 20 years, reverse engeneering these machines is next to impossible.
This goes beyond professionalism. This man and his team IS a full professional institution on these topics. This is how informative channels should be.
The naming schemes really are a mess lol. The 1st guilty party are the industry players for failing to create a proper standard and then is the less tech savvy tech media that don't clarify these distinctions. Awesome vídeo as always :)
The names are a mess because they’re meaningless at this point. Designs are diverging based on proprietary innovations so there’s no point standardizing.
Number of transistors on a chip would probably be a better indicator rather than the industry jargon being used. Most people seem to think that 2nm is the limits of Moore's law when it is not even close to the truth. They could stall at 2nm and still get more transistors in there. I think there is a 12,000 more increase to be had with out any sorts of fancy three dimensional architecture. I bet we will still be talking about its send in 20 years time.
Those transistors at 8:28 perplex me! I presume gray is silicon substrate, I guess blue is the insulator (either SiO2 or SiliconNitride), which makes purple the conductor (probably poly silicon or a metal). So why is the gray (mono silicon) touching the gate conductor? So are they not showing the drain and source perhaps? I don't get what we are looking at! Even the planar FET doesn't make sense.
Hey TechTechPotatoe. Just found your channel and finding all this in depth CPU talk great. I actually have been meaning to find a channel or a resource that talks about this specifically. Thank you for covering it. I also think it is so cool how you have been invited to places like IBM :). Keep up the great work from another techie that has big aspirations as well.
Wonderful content, man. Super informative. Love both the cursory introduction to some technical info as well as the deeper look into history, design, and marketing. Not a careless word thrown in! You do a great job and gained a new subscriber!
You really have most intriguing content. I saw you in the "Moore's Law is Dead" episode first - I loved this episode, so I also followed you on your channel.
Most that claim it is dead do not even know what it means and they some how think it has to do with with industry jargon that is being used such as 7nm and 2nm. Do you remember when frequency used to be the big thing in industry.
Ian, small remark, the Wilton facility does not build EUV machines. It produces parts for the ASML Scanner like reticle stages and certain clamping mechanisms. The full EUV machines (Scanner + EUV light source) are build in Veldhoven the Netherlands. ASML San Diego (formerly Cymer) builds big part of the EUV light source. So if you really want to see some EUV technology you need to go to San Diego, not Wilton. Just mentioning it to prevent disappointment.
@@TechTechPotato Yes of parts (related to the Scanner) that end up into the full EUV machine, but they don't do actual work on the 'full' EUV light source. But still a super opportunity to visit that site!.
@@TechTechPotato All EUV used in the U.S are made in the U.S. That was the agreement in the first place. The EUV itself is an American technology. www.eetimes.com/u-s-gives-ok-to-asml-on-euv-effort/
@@someone5582 Not really a surprise a 22 year old article (containing multiple errors btw) does not reflect the current reality. The story might state the intentions that they had at that time, but reality turned out differently. To give you an idea, there was not just 1 EUV light source under development, but at least 3. In the end it was a close race between Cymer and Gigaphoton who would make the first technically and commercially viable light source. Eventually ASML went all in on Cymer, who was developing the light source the article is probably referring to. As development went way to slow, ASML bought Cymer in 2013 and moved a lot of the research facilities (including most of the software development needed) to the Netherlands. Only the last couple of years things are moving back to ASML San Diego (formerly Cymer) again. As a result you will find many parts of the light source being designed, developed and produced in the Netherlands and some neighboring countries. E.g the modular vessel, the vacuum enclosure, where all the magic happens is build in the Netherlands by VDL , the huge laser that fires on these tiny Tin droplets is made by TRUMPF Germany, and all optical mirrors to focus and transport the light beam are created by Zeiss Germany. Intellectual property matters are not really my field of expertise, but I think it's safe to say a statement like 'EUV is American technology' (or any other country for that matter) is wrong on multiple levels. As mentioned multiple parties were trying to develop an EUV light source, the American variant as mentioned in the article is one of them, but other prototypes were developed outside of the US. The owner of the technology is the one holding it's intellectual property / patents. And after Cymer was bought by ASML these EUV patents came in the hand of ASML, look up patent US7453077B2 (EUV light source) if you want. You will see the Current Assignee is ASML Netherlands BV. And yes agreements where made during this acquisition of Cymer by ASML. As the US government considered the technology sensitive for national security ASML is by agreement not allowed to export these EUV light sources to certain listed countries/regimes without permission from the US. The whole political story is way more complicated then this (as ASML is in fact only depends on a GO for delivery from the Dutch government and not from the US one), but it will give you an idea of what is going on. Also be clear the article and myself are only talking about the EUV light source. A working machine consists of a scanner with a light source attached. You need both. As the US has no say in the scanner part and non-EUV lightsources, DUV machines (scanners with a different, slightly older technology light source) are (still) sold to China.
It's a bit unexpected to see die shrinking is still in full speed Thanks for your informative video and hope we can keep getting higher computation performance! Everyone loves a cute potato, munching wafers and naturally your channel!
I learned when I was 8 (28 now) that technology is doubling every 9 months. For the last few years it seemed like that wasnt the case. Now it's back on track. I cant wait til I'm 48 to see what its gonna be like then.
This is extremely good news, it's getting exponentially harder to scale down even further as we are reaching quantum limits for electrons. The distances between certain features within the transistors can be measured in atoms... (I think IBM made a video/animation using 8 or so atoms in a stickman configuration) Even assuming you could get over the quantum tunneling effects, we cant build circuits smaller than the size of an atom, we would need a breakthrough in optical or full quantum computing. Truly amazing, the cutting edge of applied physics.
I worked for Altera for 6 years, long before they became Intel FPGA, and the nm 'measurements' bandied around were largely dictated by the marketing departments even then. Getting an apples to apples comparison between manufacturers was tricky then, probably exponentially harder now.
I think the only measurement that should be used to describe process technology generation is transistors per quare millimeter because that's the only metric that cannot be twisted by the marketing department. Even there you should also include the frequency you can run those transistors.
@@TechTechPotato If you want accurate results, you could specify one exact transistor type for that metric. I think that even if the metric used *any type* the results would be much better than current "nm" names. Another option is just to forget about the process level comparisions and just get chip manufacturers to tell the total transistor count for a chip in addition to chip area and we could just compute average transistors per square millimeter over the whole chip. That would better reflect the fact that the process technology is not the only thing that matters for actual performance and that chips are not just transistors only.
Just discovered your channel, great video! I'm a PhD MatSci student working on alternate interconnect metals and it's nice to have something somewhat relevant to watch while I'm in lab :)
Sounds like we are getting close to measuring process nodes in picometers. At that point Ian's new tag line could be, "I have pica for picometers" ... Sounds like it should be on a cereal box.
No not really the smallest a transistor can get is around 0.8 nm between source and drain which are 3 silicon atoms in a row and this is without doting the material
A silicon atom is 0.21nm, and you need a few of them, due to doping with other atoms to create the PNP setup needed for a transistor to work. But they are building in 3d and only measure the horizontal plane. So maybe towers of 0.21nm wide could be the most dense they can get.
@@SurelyYewJest My guess is that they will probably take him to a conference room where they have everything they want him to record ready to present and then provide him with pre-recorded videos of the other areas of the lab that has been approved for release.
What’s the guarantee that every single one of those transistors will work? I bet it’s like Christmas lights. There’s bound to be one slightly dimmer or not working which can affect performance. Impurities of materials are almost impossible to eliminate.
Be sure to see CREE/Wolfspeeds new 200mm SiC fab when you are in New York. I would love to hear your thoughts on SiC for high voltage power management.
I realize who you are now within a minute of starting this video; the first video of yours I've seen now. Pleasure to meet you Dr. Ian Cutress. I'm probably older than you and finally in a position I can reliably afford to go to college for IT and potentially Computer Science to continue digging myself out of family influenced poverty. I'll gladly be subscribing and looking forward to learning all I can from you.
Glad you put this out. I retired from the semiconductor industry in 2005. At that time it was obvious we had gone as far as we could with conventional photo printing and quantum effects were impacting transistor design for lower power circuits. Your description of the meaning of X nm's helped me understand the pivot that technology has taken since my retirement.
So you know the foot/meter conversion ratio but you don't know the thumbnail/mm² one? I thought doctors were supposed to be smart. For real though, love your content.
I am an electronics engineer with a marketing qualification but I HATE it when companies engage in "specmanship". It takes me back to the early days of AMD when their chips were given a number which was not the CPU clock but the speed that an Intel chip would have to run at to have the same performance. Why the companies try this on I don't know but it always ends up in some sort of farce !!
We need more technical content like this from people with technical degrees. I'm not saying degrees are everything, but when you spend years of your life learning about math and science in a formal setting it gives you a perspective that is uncommon among people who lack a formal education. Lots of stuff on the internet about tech but few really have the knowledge to describe the details accurately. Ian is one of the few.
There's plenty more room: That is a reference to Richard Feynman, the father of nanotechnology, right? In a seminal paper called "There's plenty more room at the bottom" he showed that some materials could be created by stacking atoms one by one, or molecules one by one, creating materials with the thickness of an atom. Guess his game has been taken to the next level nowadays.
this is ridiculous. no one needs 2nm procesors, its simply to small. this is where government needs to step in and make it stop, because science is going to far
Our fab is also working on a 2nm node length too. One of the chief issues we are facing at this length are quantum mechanical properties, as the electron crosses over the threshold only to become a positron and no longer an electron.
Love these videos but they make me feel ancient. I was a electronics technician for almost 30 years and have seen so many changes for the better. Example: The first military piece of equipment I worked on had a test set the size of a refrigerator and the program had to be loaded with floppy disks that were the size of an LP. This airplane (and test set) is still in use.
I can’t even wrap my head around 2nm lithography, but I suspect it’s some trick where it’s really 5-7nm but some crazy stacking it offset gimmick but we will find out eventually. Even 5nm doesn’t make sense to me.
Ever since 14nm and the first finfets, the naming hasn't matched any real physical dimension because the transistor went 3d. This naming is meant to imply a theoretical 2d transistor of that size. At 2nm we move beyond finfets to nanosheets and there are multiple generations of that to come
Thanks for breaking the big numbers down for us. But the B&W pic at 2:09 is actually my root canal picture! Oh - and that black cat is bad luck - might wanna trade it in for a white one. lol And I was just imagining you taking the black cat w/ you on a tour of an IBM transistor clean room facility at 4:32 where they wear those white suits - and it jumping from your arms - you'd never catch it before a 100 million cat hairs came loose!
Very nice video, thnx for posting. However, at ASML Wilton they only make the Top Module for EUV, consisting of the Reticle Handler and Reticle Stage. If you really want to see the complete build of an EUV system, you have to visit ASML in Veldhoven, The Netherlands. And beyond multiple patterning on an EUV system is of course the introduction of the High NA (0.55) EUV system. I agree with you that we will see some interesting shrink in the near future.
The Cat Tax was actually quite reasonable, until I saw the slippers! EEK Get yourself some Uggboots, man! Loved the video. Although I do software architecture, not chip architecture, I still found this fascinating. Thanks.
Interesting channel you have my sub! Some people bash IBM, but i admire theirs cpu architecture, they have even control of bitshift against radiation. IBM mainframes are big number crunching machine , which can run multiple Linuxes, multiple ethernet ports, multiple ram (petabytes!) and more other stuff which you can attach to IBM mainframe.
![[32] Ian Interviews: Pat Gelsinger, Intel CEO](/img/1.gif)
When you said about 333 million transitors per mm square that honestly broke my brain. Utterly astonishing engineering going on.
It still blows my mind that we're in the billions of transistors on CPUs now, basically every single one has to work or the whole chip is useless, and these things run for *decades*. I don't know of any other thing we make as a species that's good for quadrillions of operations with zero maintenance.
That's also peak.
Intel's 14nm wasn't twice as dense as TSMC's 14nm at the end of the day. If it was there's no way Ryzen would have been competitive.
Just keep in mind that these situations are being designed by individuals and then being taken and tweaked for scalability by others. Cooperation is the real magic of Engineering.
Just don't try to count them by hand.
@@Teth47 I would imagine, that with that scale of transistors, and to have a faulty one kill a whole chip, they will build a few redundancies in, so that if a portion of the chip has a fault, they can just fuse it out, and have a backup circuit take up the slack. At least, that's how I would do it, if designing something with that number of potential failure points. I'd build redundancies in so chips could be "saved" even if one critical part had a fault, and a have a fuse map to choose which parts to enable/disable. Sure, it's eats up some silicon space, but if you has even just 1% used for backup circuits, and it could rescue otherwise failed/faulty chips, I think it would be worth it.
For ~40 years,I worked at the IBM foundry where they built/tested semiconductors. (wrote software to run the line) IBM no longer manufactures their own chips...but they still design them and monitor every step of the manufacturing process. It is interesting that most folks dont even think of IBM when "tech companies" are discussed.
I guess them pulling out of selling office/consumer machines to focus on cloud/enterprise hardware and R&D pushed them out of focus for most people...the name is well known, but many people have no idea what they're on about these days because there's little to no (obvious) presence outside of IT space
When you think of IBM, you'll think of the physical products they produced with their name on it. Things like early PCs, not modern tech.
right, what ever happened to IBM? They used to be THE tech leader, but now who knows IBM? They design chips, they have AI, and they are working on quantum computing. Strange.
@@ketzbook cutting edge tech isnt meant for consumers. microsoft is a consumer based company along with apple/etc... theyre focus is consumer userability not pushing the limits of science.
Except when it's about the Thinkpad. The world hasn't completely acquiesce credit to Lenovo except for bad designs. 😂
Really really appreciate that you've got links to everything. What most informative channels should do
ddr 6 oh common it will be ddr 7 lol
its useless links but ..
Some other wouldn't even give source. I flag them as misinformation
@@Mr11ESSE111 don't say that the person put effort on it you'll make the person sad :'(
@@thefirstsin efforts for useless links again
4:46 - I worked at IBM a few years ago (IBM Software Lab). And I remember quite distinctly that we were strongly encouraged to come up with patent applications for the company. Anything was fine as long as it was patentable. We were rewarded with a salary bonus for a successful patent application.
Sounds like they were getting over on you and all there employees 😂😂😂
@@stephenmontez6754 patents were properly filled with all the inventors listed
I love these videos where you explain the details of how the industry and manufacturing process works. Ive learned a lot from watching your videos
Lithography. You "print" with an acid resistant and removable material, give it a dunk in acid then remove the printed material. There are more complicated processes. The mechanical tolerances of the "printer" determine how small you can print. The failure rate multiplied by the die size will determine the yield rate because of the two dimensional nature.
hey Shank, a small world! We caught you there 😜
Same here. Thanks !
@Kenn Honson X .
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Wiiu portable running off a watch battery is now possible
Seems like only yesterday I was a process engineer diddling about to keep uniformity
I'm still waiting for that carbon nanotube revolution ¯\_(ツ)_/¯
graphene turns out to be hard to make at scale.
Yassss
There's some promising developments in increasing the length they can grow carbon nanotubes, but we still have a long way to go before we're consistently growing nanotubes of indefinite length.
Won't happen without a process scaling like lithography did.
Moore's law was never about this industry jargon of 7nm and 2nm. Those are not the defining limits to how many transistors can be put put on 1000mm square integrated circuit.
We could very well have another 12000 times increase in the number of transistors on chips and that is without the actual chip getting larger.
So we may have another 12 to 16 doublings ahead of us in terms of how many transistors can be crammed on to a chip.
So your Nanotube revolution maybe at some stage play a part.
Glad to have discovered a channel that actually gets the current state of processors and goes into as much detail as possible. Great and well researched content!
that Jim Keller clip really puts things into perspective.
I don't think that removing one bottleneck solve the scaling issue though. The resolution of the lithography process might be high enough to keep increasing the transistor density, but does that mean that it's practical to do so? As far as I understand the real issue might not be Moore's law, but Dennard scaling. If the power density gets to a point where we can't find ways to practically cool a silicon die, we're just hitting a different bottleneck instead.
@@cosmiczeppelin there's always new challenges to overcome, but the important bit is that there's no fundamental limit that we're hitting yet.
@@cosmiczeppelin we can always run the coolant through the chip itself. Packaging might get a bit complicated though
It was explained very well. Guess I learned some stuff.
@@Greitone oh jesus christ, i rue the day that microfluidics enter the semiconductor scene for... cooling...
Thanks for explaining the disconnection from different companies "nanometers" and the real physical dimensions. I think this is what a lot of people don't understand.
Agree, I always assumed it was directly proportional to density.
This channel is amazing, you’re talking about all the interesting things I’m into and I can’t find other places
I'd care more about the fact Jim Keller used Comic Sans for his presentation if he wasn't talking about such complex things. The absurdity of describing such technology in Comic Sans is actually very fitting
I believe it's on purpose
Comic sans is more a cultural backlash from graphist like me due to the democratization of fonts and the loss of power of the expert, it became the symbol typographer rallyed around for it's misused in some context, however that reputation is far fetch and the mockery for using it is a bit overdone, comic sans is basically normal people trying to inject humanity against overly formal font design (which is why the font was created in a first place, because using times new roman in a kids birthday card was equally stupid). Nobody can tell me helvetica is a font designed to be at human scale.
@@NeoShameMan Comic Sans was created as the screen font for Microsoft Bob. It was never intended for regular use. Using it for technical purposes is funny at first but actually distracts from the content. I don’t know what you mean by human scale, but Helvetica is one of the classic typefaces of the 20th century. Love it or hate it, it should not be dismissed. I can highly recommend the “Helvetica” documentary that came out several years ago.
@@germansnowman i know all the historical details of these two fonts, even why p and q are different in comic sans and why the middle bar of the m is crooked, i havw entire book about helvetica and how pauler scher tried so hard to avoid that damn overuse fonts, o know the context, a single god damn documentary won't change my mind 😂
The reputation that comic sans is hard to read is all made up, sans serif font use to be said the same, now they are standard. history is much more nuanced, and contextual cultural aspect add complexity, the but give you the full picture.
@@NeoShameMan Fair enough. I just thought you did not know all that because you said that Comic Sans was made for kindergarten posters. In any case, I did not say Comic Sans is hard to read; my point is that typography should serve the content, and typefaces convey certain moods and connotations. If one knows the rules, it’s OK to break them intentionally. However, I thought that the original Higgs Boson presentation by CERN was very much devalued by its unironic (and very likely uneducated) use of Comic Sans.
Jim Keller always floors me with how he can talk about such high-minded concepts like they are simple and elegant. I also paid the cat tax.
I mean - regarding this - his comic sans represents the ultimate swag
What is cat tax
But Moore’s Law is still dead as an economic law
@@BirdTho Video chapter dedicated to his cat. Pay the tax or cat will bite you.
Except he kept calling a cross an 'x'.
The content on this channel is so consistently high-quality that I am upgrading from Bulldozer to Nehalem
Interesting stuff. Didn’t realise how significant EUV has been. Bit of a holy grail it sounds like. I remember reading articles about it being prototyped.
i'm more impressed that they managed off-state leakage current than being able to print small features
Imagine not only being super smart, but also being so cool you get open invitations to industry leading research facilities, AND having an adorable cat
By then you have achieved (unlocked!?) Bond Villain status 🧐
Oh man I only have a cat
Does that cat even realize his owner is so smart!!?
not that smart if still not healthy vegan in 2021 🙄🤦🏻
cats are not adorable they are the worse pet, not loyal, wont help you, wont stand by you, wont protect you, they are a LAZY persons pet as they just go do what they want. not to mention they kill other animals just for sport, you say dogs do? no dogs can be trained to not do or to do anything, cats ingeneral cant be trained to do hardly anything, cat ppl are just the worse
It's nice to know not only what Intel/TSMC/AMD does, but also what is actually researched, great video. Here are my 2 cents for the algorithm, this channel needs to grow.
Keep in mind that the minimum feature size (2nm) is *much* smaller than the actual transistors. At 333M transistors per square mm, the transistor average spacing is 55nm. That is about 260 silicon atom diameters, while 2nm is only 9.5 atomic diameters.
Keep in mind one of the first things I mention in the video is that it's only a name.
@@TechTechPotato
Yes, I just wanted the viewers to realize how misleading the names are. The chart of transistor densities that you showed, does convey the inconsistencies between manufacturers, but not the magnitude of the difference between feature and transistor size. If you read through comments here and elsewhere, you find that many people still think the names are the transistor sizes.
Judging by your comment, it appeared as if you hadn't watched the video. Which is what a lot of people making those sorts of comments you're referring to end up doing as well.
@@TechTechPotato
When I find other videos on the topic, I'm recommending to viewers that they go to your channel for better detailed information.
@@TechTechPotatoan engineer should not pick-up Marketing speek too much
Would be nice if the industry moved over to transistor density of the node used instead of the now arbitrary nm.
transistor density also isn't a single value because there's high density, high performance and low power libraries, each with different densities.
Marketing strongly disagrees with you, until they can find a metric that makes their product look undoubtedly superior to competitors..
Dziękujemy.
High-quality content on Tech Tech Potato. I went into the description to find Jim Keller's video and it was actually cited properly!
By chance this video was suggested, and as a former semi worker my mind is officially blown. At RCA Findlay (later Harris) we advanced to 0.5 um using i-line Canon FPA 1500 steppers back in the early 1990s; that was a big advance from the MPA-501 that were only 1.5 um line width. Thanks for this video.
IBM is the O.G in Tech and R&D .
The real tech in semiconductors is from ASML though. They made these EUV machines that make the chips, the only one that can.
ASML have been the silent driving force behind all the innovation over the last 10 to 20 years.
That is the lithography machines that print the designs on the silicon wafer.
If you nuke this 1 company and all its people, research. We go back like 10 to 20 years, reverse engeneering these machines is next to impossible.
what is O.G
@@HalitZiyaKARTAL it means “ Original Gangster “
This goes beyond professionalism.
This man and his team IS a full professional institution on these topics. This is how informative channels should be.
I feel like this content is filling a Coreteks/Adored hole, a potato size hole.
Notice outro sounds has that Coretex vibe. Am expecting a groveling voice and none comes
I miss Jim from adoredtv.
@@mrrolandlawrence Jim is now freethinker, he debunks conspiracy theories, it's really amusing.
much better than Coreteks IMHO
Interestingly, "patata" which literally means potato in Spanish is also used as slang for heart. "Me llegó a la patata" = "It reached my heart"
I think that video had exactly the right amount of detail for me. All the visual explanation really helped that a lot
The naming schemes really are a mess lol. The 1st guilty party are the industry players for failing to create a proper standard and then is the less tech savvy tech media that don't clarify these distinctions.
Awesome vídeo as always :)
Hey, at least Intel never released a 14nm 3.2 gen 2x2 process. Count your blessings!
The names are a mess because they’re meaningless at this point. Designs are diverging based on proprietary innovations so there’s no point standardizing.
Number of transistors on a chip would probably be a better indicator rather than the industry jargon being used.
Most people seem to think that 2nm is the limits of Moore's law when it is not even close to the truth.
They could stall at 2nm and still get more transistors in there. I think there is a 12,000 more increase to be had with out any sorts of fancy three dimensional architecture.
I bet we will still be talking about its send in 20 years time.
Those transistors at 8:28 perplex me! I presume gray is silicon substrate, I guess blue is the insulator (either SiO2 or SiliconNitride), which makes purple the conductor (probably poly silicon or a metal). So why is the gray (mono silicon) touching the gate conductor? So are they not showing the drain and source perhaps? I don't get what we are looking at! Even the planar FET doesn't make sense.
lol, don't use the two syllable slang (short version) for "transistors" otherwise google marks it as hate speech and deletes the comment.
Never watched your channel before, it just showed up on my feed and I had to give you some kudos on the title.
This just came up in recommended, man I'm glad it did. You've got some brilliant content.
Hey TechTechPotatoe. Just found your channel and finding all this in depth CPU talk great. I actually have been meaning to find a channel or a resource that talks about this specifically. Thank you for covering it. I also think it is so cool how you have been invited to places like IBM :). Keep up the great work from another techie that has big aspirations as well.
Wonderful content, man. Super informative. Love both the cursory introduction to some technical info as well as the deeper look into history, design, and marketing. Not a careless word thrown in! You do a great job and gained a new subscriber!
You really have most intriguing content. I saw you in the "Moore's Law is Dead" episode first - I loved this episode, so I also followed you on your channel.
Do you have a link
Most that claim it is dead do not even know what it means and they some how think it has to do with with industry jargon that is being used such as 7nm and 2nm.
Do you remember when frequency used to be the big thing in industry.
Ian, small remark, the Wilton facility does not build EUV machines. It produces parts for the ASML Scanner like reticle stages and certain clamping mechanisms. The full EUV machines (Scanner + EUV light source) are build in Veldhoven the Netherlands. ASML San Diego (formerly Cymer) builds big part of the EUV light source. So if you really want to see some EUV technology you need to go to San Diego, not Wilton. Just mentioning it to prevent disappointment.
Huh. Their PR told me the Wilton plant does a lot of EUV assembly.
@@TechTechPotato Yes of parts (related to the Scanner) that end up into the full EUV machine, but they don't do actual work on the 'full' EUV light source. But still a super opportunity to visit that site!.
@@TechTechPotato All EUV used in the U.S are made in the U.S. That was the agreement in the first place. The EUV itself is an American technology.
www.eetimes.com/u-s-gives-ok-to-asml-on-euv-effort/
@@someone5582 Not really a surprise a 22 year old article (containing multiple errors btw) does not reflect the current reality. The story might state the intentions that they had at that time, but reality turned out differently. To give you an idea, there was not just 1 EUV light source under development, but at least 3. In the end it was a close race between Cymer and Gigaphoton who would make the first technically and commercially viable light source.
Eventually ASML went all in on Cymer, who was developing the light source the article is probably referring to. As development went way to slow, ASML bought Cymer in 2013 and moved a lot of the research facilities (including most of the software development needed) to the Netherlands. Only the last couple of years things are moving back to ASML San Diego (formerly Cymer) again. As a result you will find many parts of the light source being designed, developed and produced in the Netherlands and some neighboring countries. E.g the modular vessel, the vacuum enclosure, where all the magic happens is build in the Netherlands by VDL , the huge laser that fires on these tiny Tin droplets is made by TRUMPF Germany, and all optical mirrors to focus and transport the light beam are created by Zeiss Germany.
Intellectual property matters are not really my field of expertise, but I think it's safe to say a statement like 'EUV is American technology' (or any other country for that matter) is wrong on multiple levels. As mentioned multiple parties were trying to develop an EUV light source, the American variant as mentioned in the article is one of them, but other prototypes were developed outside of the US. The owner of the technology is the one holding it's intellectual property / patents. And after Cymer was bought by ASML these EUV patents came in the hand of ASML, look up patent US7453077B2 (EUV light source) if you want. You will see the Current Assignee is ASML Netherlands BV.
And yes agreements where made during this acquisition of Cymer by ASML. As the US government considered the technology sensitive for national security ASML is by agreement not allowed to export these EUV light sources to certain listed countries/regimes without permission from the US. The whole political story is way more complicated then this (as ASML is in fact only depends on a GO for delivery from the Dutch government and not from the US one), but it will give you an idea of what is going on.
Also be clear the article and myself are only talking about the EUV light source. A working machine consists of a scanner with a light source attached. You need both. As the US has no say in the scanner part and non-EUV lightsources, DUV machines (scanners with a different, slightly older technology light source) are (still) sold to China.
Thanks for the content Ian, here's one for the algorithm :D
Great video with very interesting insights into this area. Certainly one of the better explanations about the whole nanometer naming process.
It's a bit unexpected to see die shrinking is still in full speed
Thanks for your informative video and hope we can keep getting higher computation performance!
Everyone loves a cute potato, munching wafers and naturally your channel!
I learned when I was 8 (28 now) that technology is doubling every 9 months. For the last few years it seemed like that wasnt the case. Now it's back on track. I cant wait til I'm 48 to see what its gonna be like then.
I understood 4 whole words in this whole video but found it all very interesting. For once the RUclips algorithm made a great recommendation.
Yes, indubitably
First video of yours i have seen. Instantly subscribed, fantastic information, equally well explained. Love it!
what I think ? I think this Channel Deserve more Love And Attention , Great job keep it going please !
Solid video, great tables and references. Keep up the good work.
dude, that cat looks like he's gonna have you as it's dinner.
Honestly I wasn't going to watch the whole video, just wanted to post a Team Red (AMD) comment.. now I have to watch it all to see the cat.
Thank you for making this video
It really helped understanding some very important details
This is extremely good news, it's getting exponentially harder to scale down even further as we are reaching quantum limits for electrons. The distances between certain features within the transistors can be measured in atoms... (I think IBM made a video/animation using 8 or so atoms in a stickman configuration)
Even assuming you could get over the quantum tunneling effects, we cant build circuits smaller than the size of an atom, we would need a breakthrough in optical or full quantum computing. Truly amazing, the cutting edge of applied physics.
I love the decriptions below the video. The links, the papers are so informative. Thanks your content its really edu-tainment.
I worked for Altera for 6 years, long before they became Intel FPGA, and the nm 'measurements' bandied around were largely dictated by the marketing departments even then. Getting an apples to apples comparison between manufacturers was tricky then, probably exponentially harder now.
People have mistaken taken Moore's law to mean the increase in computing speed and other industry jargon.
I think the only measurement that should be used to describe process technology generation is transistors per quare millimeter because that's the only metric that cannot be twisted by the marketing department. Even there you should also include the frequency you can run those transistors.
The problem is that it can be manipulated. What types of transistors - simple ones or large flip-flops? What's the right ratio?
@@TechTechPotato If you want accurate results, you could specify one exact transistor type for that metric. I think that even if the metric used *any type* the results would be much better than current "nm" names.
Another option is just to forget about the process level comparisions and just get chip manufacturers to tell the total transistor count for a chip in addition to chip area and we could just compute average transistors per square millimeter over the whole chip. That would better reflect the fact that the process technology is not the only thing that matters for actual performance and that chips are not just transistors only.
Damn, Dr. Potato/Cutress just did it again, answered a ton of questions I didn't know I was interested in!
Just discovered your channel, great video! I'm a PhD MatSci student working on alternate interconnect metals and it's nice to have something somewhat relevant to watch while I'm in lab :)
Sounds like we are getting close to measuring process nodes in picometers. At that point Ian's new tag line could be, "I have pica for picometers" ... Sounds like it should be on a cereal box.
Nah, they will go to angstroms (a tenth of a nm). Plus they will hit the limit soon on size reduction
No not really the smallest a transistor can get is around 0.8 nm between source and drain which are 3 silicon atoms in a row and this is without doting the material
we cant, the atoms are bigger than picometers
There’s actually very little room left at the bottom. Advances are now majority driven by design rather than scaling. Case in point, this IBM design.
A silicon atom is 0.21nm, and you need a few of them, due to doping with other atoms to create the PNP setup needed for a transistor to work.
But they are building in 3d and only measure the horizontal plane. So maybe towers of 0.21nm wide could be the most dense they can get.
Excellent Video. Thank you for sharing.
Well, the key question for is "how's the performance?" And a concrete answer to that question doesn't exist yet. But hopefully it will be good.
Your videos are informative, interesting and easy to listen to. Thanks for the videos!
You NEED to go visit all of those fabs ASAP and produce videos, that would be absolute prime content!
HAH, good luck getting cameras in to record much. Even HVM fabs are heavily locked down. Research fabs?
@@SurelyYewJest My guess is that they will probably take him to a conference room where they have everything they want him to record ready to present and then provide him with pre-recorded videos of the other areas of the lab that has been approved for release.
Thanks for explaining the very complicated topic in a simple way!
Interesting video! Thank you Ian.
What’s the guarantee that every single one of those transistors will work? I bet it’s like Christmas lights. There’s bound to be one slightly dimmer or not working which can affect performance. Impurities of materials are almost impossible to eliminate.
Be sure to see CREE/Wolfspeeds new 200mm SiC fab when you are in New York. I would love to hear your thoughts on SiC for high voltage power management.
As a computer / electrical engineer that studied this exact thing pre-2000 it's amazing to see just how far things have progressed.
Same here. Only I received my degrees in 1983.
Love the video, this is very, very interesting.
Indeed! Very useful!
Just found you, sir, you have a new sub.... also very excited about 2nm chips.
> Moore Room
hehe
moore didn't say you couldn't do 2 nm he just said 6 nm was the size of a single silicon atom that's all
I realize who you are now within a minute of starting this video; the first video of yours I've seen now. Pleasure to meet you Dr. Ian Cutress. I'm probably older than you and finally in a position I can reliably afford to go to college for IT and potentially Computer Science to continue digging myself out of family influenced poverty. I'll gladly be subscribing and looking forward to learning all I can from you.
I don't really quite get everything, but i know the algorithm just struck gold recommending this channel.
Glad you put this out. I retired from the semiconductor industry in 2005. At that time it was obvious we had gone as far as we could with conventional photo printing and quantum effects were impacting transistor design for lower power circuits. Your description of the meaning of X nm's helped me understand the pivot that technology has taken since my retirement.
I really appreciate the reference in the title to my boy Richard Feynman! The guy was a genius
@@lordjaashin because he wants?
epic video my man. Pleasure to watch as you have a very smooth and informative way to just lay it all out plainly. Thank you :)
So you know the foot/meter conversion ratio but you don't know the thumbnail/mm² one? I thought doctors were supposed to be smart.
For real though, love your content.
This is my first time watching your channel. Immediately subbed.
Came for the tech talk, stayed for the kitty (and those dope slippers!)
I just love this whole channel now, keep sharing knowledge! Please!
I'm here for the cat tbh (love what you're doing with the channel).
Really good video. I wonder what the yields on these things are?
This video in a nutshell: Everything is a lie, and you can't trust anything.
Thank you for saving 15 minutes of my life.
@@J235304204 Still worth watching, I think. It was interesting to get some insider perspective on _why_ it may largely be marketing hype.
I am an electronics engineer with a marketing qualification but I HATE it when companies engage in "specmanship". It takes me back to the early days of AMD when their chips were given a number which was not the CPU clock but the speed that an Intel chip would have to run at to have the same performance. Why the companies try this on I don't know but it always ends up in some sort of farce !!
For cars there was a slogan 3=6 due to 2-stroke vs 4-stroke😮. Was in the 1950s
We need more technical content like this from people with technical degrees. I'm not saying degrees are everything, but when you spend years of your life learning about math and science in a formal setting it gives you a perspective that is uncommon among people who lack a formal education.
Lots of stuff on the internet about tech but few really have the knowledge to describe the details accurately. Ian is one of the few.
I really dislike the misleading naming of process nodes.
Sheldon Cooper does not like your t-shirt
With reason I would say haha
Always nice to find someone running a channel about semi manufacturing who knows what they’re talking about. 👍
Miaou. SCRATCH! No kitty! It's not that kind of wire, it's nano wire!! :0
There's plenty more room: That is a reference to Richard Feynman, the father of nanotechnology, right? In a seminal paper called "There's plenty more room at the bottom" he showed that some materials could be created by stacking atoms one by one, or molecules one by one, creating materials with the thickness of an atom. Guess his game has been taken to the next level nowadays.
Yup. And Moore is a reference to Gordon Moore.
@@TechTechPotato thanks, Moore got me guessing , I had no idea which one it was
As in, Moore's Law
When public transport is back up, you should try to go to the root of ASML / home of euv, here in The Netherlands at Eindhoven
I love your channel ... an interview with Jim Keller on this channel will be fabulous
:)
this is ridiculous. no one needs 2nm procesors, its simply to small. this is where government needs to step in and make it stop, because science is going to far
calm down bro we are getting very close to size of atoms surely it will stop one dayy? right?
Limited only by your imagination.
@@jamesdriscoll_tmp1515 if we can shrink atoms then yes
@@niggacockball7995 if we are limited to atoms
@@jamesdriscoll_tmp1515 what are you gonna do? build a transistor out of photons?
8:40: What's "LEA-Ceti"?
CEA-Leti*
@@TechTechPotato Haha, thank you. h/t Spilliam Wooner.
I love how they used Comic Sans for the presentation
Our fab is also working on a 2nm node length too. One of the chief issues we are facing at this length are quantum mechanical properties, as the electron crosses over the threshold only to become a positron and no longer an electron.
Love these videos but they make me feel ancient. I was a electronics technician for almost 30 years and have seen so many changes for the better. Example: The first military piece of equipment I worked on had a test set the size of a refrigerator and the program had to be loaded with floppy disks that were the size of an LP. This airplane (and test set) is still in use.
I can’t even wrap my head around 2nm lithography, but I suspect it’s some trick where it’s really 5-7nm but some crazy stacking it offset gimmick but we will find out eventually. Even 5nm doesn’t make sense to me.
Ever since 14nm and the first finfets, the naming hasn't matched any real physical dimension because the transistor went 3d. This naming is meant to imply a theoretical 2d transistor of that size. At 2nm we move beyond finfets to nanosheets and there are multiple generations of that to come
Thanks for breaking the big numbers down for us. But the B&W pic at 2:09 is actually my root canal picture! Oh - and that black cat is bad luck - might wanna trade it in for a white one. lol And I was just imagining you taking the black cat w/ you on a tour of an IBM transistor clean room facility at 4:32 where they wear those white suits - and it jumping from your arms - you'd never catch it before a 100 million cat hairs came loose!
Very nice video, thnx for posting. However, at ASML Wilton they only make the Top Module for EUV, consisting of the Reticle Handler and Reticle Stage. If you really want to see the complete build of an EUV system, you have to visit ASML in Veldhoven, The Netherlands. And beyond multiple patterning on an EUV system is of course the introduction of the High NA (0.55) EUV system. I agree with you that we will see some interesting shrink in the near future.
Every video is a banger. Congrats on the growth bossman.
Nice topic! more on this stuff please!
awesome video. glad to have found this channel.
The Cat Tax was actually quite reasonable, until I saw the slippers! EEK Get yourself some Uggboots, man! Loved the video. Although I do software architecture, not chip architecture, I still found this fascinating. Thanks.
Actually learned a lot about new fab tech on this video.
I can listen to you all day talking about transistors.
just discovered this channel. I’ll pay attention. Subscribed.
Interesting channel you have my sub! Some people bash IBM, but i admire theirs cpu architecture, they have even control of bitshift against radiation. IBM mainframes are big number crunching machine , which can run multiple Linuxes, multiple ethernet ports, multiple ram (petabytes!) and more other stuff which you can attach to IBM mainframe.