@@mduckernz I'd think hard x-rays are hard enough to focus and control exposure. Maybe taking a page out of cancer radiotherapy, a linear accelerator that can accelerate x-rays, electrons, or protons in a focused manner is a possibility. I'm not sure how those particles work for photolithography, maybe new resists needs to be invented and modification of the LINAC machine. I know there are some alternative machines not used that instead of using a large mask and exposing the whole wafer at once, work more like a CNC. Very slow but I think it was more accurate and precise? Maybe a LINAC could be focused to directly draw the design without a mask, probably extremely difficult, I don't know what's required to do that kind of precision and how the CNC type lithography machines work to begin with.
@@mduckernz Electron Beam Lithography is very interesting and can take us down to the atomic level. Look it up on Wikipedia. The only problem with EBL is that it's terribly slow, so slow that it is completely uneconomical unless someone can speed it up dramatically somehow. (Multiple beams is one idea that they are exploring.)
@@PremierSullivan Indeed, electrolithography (? Not sure if that’s a valid name for it, but you get the idea…) was the main approach that seemed viable to me. Multiple beams sounds very doable, you just need to make sure they don’t pass too close to each other so they won’t repel each other and deflect their beams. I also wonder whether you can do away with the beams, and instead use a modified resist and mask, and then bathe the silicon in electrons, treating them as if they were light. The beams approach seems likely to work, and be effective, but yeah as with you I worry about the speed of it.
I'm hearing a lot about increases in transistor density, but I have a sneaking suspicion that raw improvements in power efficiency will become more elusive over time, leading to greater considerations of things like the Landauer Limit, for instance, or in other words, leading to advanced nodes that pack tons of transistors clocked lower than current nodes, in order to avoid excessive thermal stress...Possibly leading to a revolution in software as we adjust our workloads for wider compute chips with massive parallelization capabilities, a good example of which is the rapid increase in AI based accelerators.
i'm actually not sure if that's really going to happen. power generation is ramping up exponentially with compute demand. datacenters don't seem to be more concern about power bills as much as they are concerned about squeezing the most compute possible. which means more power, as expensive as it is, is still cheaper than more compute. GPUs are getting more power hungry primarily due to exploding compute demands, and the benefits are justifying the higher power bill.
My understanding is transistor density increase usually leads to power efficiencies improvement's however they can choose to focus on more performance or more energy savings
@@kicapanmanis1060 maybe, but from what i can see this is really been driven over the last 5 or so years by an explosive demand of AI compute that just keeps skyrocketing, which is mainly done on GPUs. this would explain why GPU power consumption has taken over CPU by such a large margin.
Newsletter version: morethanmoore.substack.com/p/imecs-roadmap-to-2d-transistors-in [00:00] Teaching Rocks How To Think [00:35] www.linode.com/ttp [01:05] Who are imec? [02:35] imec Technology Forum [03:17] 2018: N7, Metal Pitch, Tracks [04:25] 2020: N5 [04:36] 2022: N3 [04:50] 2024: N2 and Gate-All-Around [05:09] 2026: A14 [06:00] 2028: A10 and Forksheets [06:36] 2030: A7 [06:49] 2032: A5 and CFETs [08:08] 2034: A3 [08:16] 2036: A2 and 2D Transistors [09:17] Other Roadmaps and VTFETs [10:04] Paper on 1nm, or not [10:46] Backside Power Delivery and Packaging? [11:20] Beyond EUV? [12:23] Cat Tax
Exciting! The amount of manpower to make chip fabrication possible is baffling. The type of structures for different nodes is also super exciting and I want to watch more about it.
Thanks Kim! Feel free to reach out if ever you're looking for sponsored content. A deeper look into the future of EDA in a chiplet and stacked world would likely go over very well
I think the real technology breakthrough would be teaching devs to stop reinventing wheels that need 10x the compute to do the same things we already could do.
Thank you Dr. Ian Cutress for bringing to Technologists minded people the latest and future updates, with such an informative but at the same time focused on essentials, manner. For reminding me , your outro track and cat's playfulness, a little something from a fellow countryman of yours .: Squarepusher (Tom Jenkinson) - Angel Integer
Thanks Ian for this. I know it might appear that EUV maybe seem like the end of the road, we may yet find a way to move the path of X-rays. It also been wonderful seeing you hanging out with Wendell, Steve, Gordon etc. I know I'm not the only person who likes that tech youtubers are a community not a competition. I see the same thing happening in the Guitar/amps/pedal/mic/music/production space with a lot of them meeting up at #42gsthree & #42gsfour
If EUV was being discussed about in the 80's, and its mass usage is in 2022, what technologies and scientifical concepts are being discussed today, apart from the one layer of atoms? If you know, that is ofcourse. I would like to imagine what they will do 50+ years from now
Artificial general intelligence. When computers can think better than humans and much faster, all bets are off. We could get a century of progress in a few years.
There is nothing beyond EUV. There is an upgrade the High NA EUV. Prototype machine are already being built but it would take a couple of years before it enters mass production. After that the industry would have to rely on multi patterning to keep scaling. This is of course the lithography side. The transistor side have a lot more avenue for squeezing density. And there is also the packaging side where a lot of research is going into increasing chip density.
I know silicon carbide is only used for power Mosfets, but you can do crazy high clock speeds with this stuff. Maybe in 50 years we might see some VLSI SiC chips, then with fabrics, assemble liitle SiC chiplets into fast little CPU's? Or not.
Super good analysis and inshowcasing what the major players are doing in this space. What would be interesting is if a review / analysis can be done of what these major fab players are doing in terms of building facilities, identifying the products they will be making, when and where (globally speaking) -- in light of the recent geopolitical turmoil, the US CHIPS act, etc.
If you wonder: there's an alternative to EUV lithography: EBL lithography (electron beam lithography). It already exists today & actually allows even smaller features than EUV, for example it already managed to produce single-atom wide features about a decade, but it does also have drawbacks: all research work I've come across indicates that it's difficult to use for mass production because results are difficult to reproduce & also costs, which is why commercial semi fabs don't use them (yet?) but some research labs do. I know some companies are trying to commercialize that but with an unknown amount of success.
The Taiwan government representative is a member of the board of directors of TSMC, and the Taiwan government will never let TSMC be completely out of government control.
It's already very much like that in every field. Billionaires are so far removed from you and I, yet wield enormous influence over both their own industries as well as govt policy. These aliens are dictating huge swathes of our lives, not least limited to the majority of our time that we spend working to make them more money. Worry not about the semiconductor foundries, they are staffed by ordinary people trying to work for a living like you and I. Worry more about the billionaires exploiting their labour and destroying the planet with overproduction, and the legions of other owners that amplify and venerate the billionaires.
Extremely interesting video. I wonder if there isn’t there more literature on the subject of scaling, metal-tracks and metal-pitch (that isn’t impossible to understand for average readers).
As long as you can get access to the papers, I’d recommend just try to read a few, you pick things up through context clues pretty quickly (keeping notes of the acronyms on the side can also help). Also, review papers and the literature review sections of thesis papers tend to be quite comprehensive and can be a good place to start when looking at a new topic
when you look at these road maps, and think what is in research vs what we get from year to year, it becomes mind boggling... that last statement was really depressing, but who knows maybe new euv technology is not the future, they might ditch it in 10 - 20 y
EUV has been a 35 year journey. Going beyond EUV has to have started today, and will take 35yr+. As far as I can tell, very little work is being done beyond EUV. High-NA sure, but that's mirrors, not sources.
There are small time research with alternatives. But there is no industry wide push to develop a technology beyond EUV. Without Industry wide coordinated effort to make something happen nothing will happen. The cost to develop something better than EUV is just to high that no single company can afford it. It has to be a team effort by everyone and even with everyone involve it will take several decades.
@@TechTechPotato I know, and that's like selling a 60kWh capacity car battery under the name "600kWh". And then imagine different manufacturers slapping random kWh numbers on their batteries to try to outcompete each other. Misusing physical quantities with a well defined meaning as marketing names is beyond misleading. Another such example that comes to mind is "resolution" of video projectors. Manufacturers market them as "4K", but it's actually just maximum supported input signal resolution and the projector then can only do a 720p image on the wall. The "native resolution" is hidden in small print.
@@ProjectPhysX Meh, it's representing the increase in density over a number of factors. Actual transistors size is just one of a handful such as, total gate area from design changes to GAA and such, space between gates, etc. You really can't just slap an accurate number anymore to actually represent the size so I'm not sure what you'd want.
@@Jaker788 of course you can put a precise number on it, and there is proposed standards to do so via transistor density. For example, count the number of transistors per mm², then calculate the average square transistor side length.
@@ProjectPhysX So you've got density down, but not quite. You have High performance cell libraries that are going to be less dense but handle more power, and there are at least a few cell libraries to choose from, all with different density and other specs. You've got ultra dense cell libraries for SRAM, stuff for logic, efficiency, custom ones for specific large customers. So even within a node there is no set density per area. There's leakage, power capability/density, efficiency, switching speed, doping materials, etc. There's a lot to a node that you just can't represent accurately. There's so much to a process node. The current naming shows up a relative improvement over the last though, and that's pretty good without making a specific claim to density. For more specific specs you can look into their datasheet and get as much info as they're willing to show the public, which isn't everything and every cell library.
On a side note about EUV, I'm surprised they are using CO2 lasers, instead of diode or fiber ones. I guess it keeps the large capacitor manufacturers in business!
At this point I would really like to know what the maximum theoretically possible density limit for transistors would be. And with "maximum theoretically possible" I mean the limit where the laws of physics say stop, not where it stops being economically viable to do because of small yield and production cost.
I think there was some experiments involving a single molecule transistor, where (as the name says) where a single molecule reliably was able to work as a switch. I think the main problem is gonna be how do we putt a lot of these in a small space and how do we make it affordable. I think the future will be a combination of different technologys like nand flash based neural networks and conventional silicon with big simulation tasks being done by quantum computers in big data centers.
We will reach a point where instead of going smaller, we start building smarter transistors. A bunch of binary transistors can do some work. But take a transistor and make it do more than 2 states? That's where the big progress will come. Neuron like computers that can dynamically adapt to different jobs, plus being able to remember information on the Neuron itself.
@@kuhluhOG I dont remember, but thats not even the point. Transirors as we know the have a size minimum, and at some point we have to make the choice between affordable chips and the most powerfull chips.
@@TechTechPotato You say that EUV wont get replaced in your lifetime, in all probability, but I posit to you that with advancements in quantum computing and AI, there will be problem solving of thousands of years of all the worlds super computers of today, done in a few hours. Quantum Computers are not really useful right now, for the most part, as I understand it, but that is set to likely change starting in a couple of years. A.I. achieved, with the AI that won at GO, what was thought to be 10 years ahead of schedule at that time. And AI researchers don't even fully understand what it going on, that's how crazy its already getting. Hopefully it doesn't end in disaster, but the advancements in intelligence itself would seem to be the thing that will allow us to go past EUV lithography, and doing so by the 2040s I'd guess.
It seems the thermal regulation of CPUs and GPUs is becoming more and more restrictive and it was suggested somewhere that it was a hinderance to AMD's 3D vcache chips. Is there any kind of microtubule type technology on the horizon that would allow water or equivalent coolant to actually flow through the meat of the die, potentially allowing them to stack more and more layers without the problem of overheating?
In microtubes there would be the limit of the possible pumping volume of the coolant and the high purity needed. Another problem would be the expansion of the coolant in high temperatures by making the chip silicone go skadoosh 💥 😂
im guessing theres good reasons why they wont be using graphene.. And im wondering if Molybdenum disulfide is a type of graphene because its a 2D layer?? another thing i thought intel once mentioned was carbon nanotubes or nanowires but i dont think its mentioned here.
In layman’s terms - we are not limited for space or power except in mobile or avionics so is the forcing function of the roadmaps - higher density and faster speed with lower power for mobile phones and weight/ space constrained applications plus perhaps cloud based servers who’s input cost has a large power component ? Whilst the shrinkage and chemistry and manufacturing tolerances are impressive , is the software keeping up ? . An 8k video from an iPhone just means that you need an 8k monitor , 8 k edit suite , 8 k graphics card , more memory , faster motherboard , more SSd storage - for what ? Many years ago Nicholas Negroponte from MIT media lab said “ we are spending vast resources developing high bandwidth interconnect networks , but hardly any on what we put in one end , and how we interpret the output “ . The old garbage in garbage out story .
Would be great if you could talk about SiC and GaN and for good measure may be even throwing in GaAs, which was long time the contender for replacing Si/SOI
How can they continue to reduce cell height (given in metal tracks not physical) without increasing width though? Isn‘t that just a geometry problem at some point? I mean one obvious thing is buried power which frees up a good amount of cell height, apart from that though, are they planning to use more metal layers for cell-level tracks or what?
Moving to Nanosheet allows for reduction for cell height because the fins are now sideways and you can just adjust channel width to reduce the cell height. Forksheet inprove this because the N channel and P channel are now side by side separated only by a barrier so two transistor are squeeze into a width of 1.5 transistor.
Also: if actual channel width gets below 5A then they really have to switch from FETs to tunneling transistors because no material or design can prevent tunneling through the channel at this scale.
Not necessarily. You put more insulator around the wires, you get less tunneling. Lower voltage, less tunneling. Lower temperature, less tunneling. Etc.
@@Anenome5 I was talking about channel width, not insulation around wires. OTOH yes, one can also try to improve channel insulation, but that has already been done A LOT & I fear there won't be any space or way left to add sufficiently more insulation around channels to prevent decrease in channel off-resistance due to tunneling of charges/holes to such a point that field effect transistors can't be used as proper logic switches anymore so that engineers will have to embrace tunneling effect by using tunneling transistors & ditch field effect transistors entirely.
Why aren't they moving to a new semi-conductor earlier? Density notwithstanding, a lower switching voltage would benefit everything, could possibly double clock speeds and halve power usage at the same time.
TSMC has started researching alternative materials. I'm guessing this will materialize as new doping materials first and some R&D into manufacturing these alternative wafers, doping materials to create a band gap if needed, how to do lithography, and characteristics. We've as a whole been researching alternatives for a while now. The hard part is finding one that is a decent semiconductor, or how to make something that's not a semiconductor actually be one with good characteristics.
@@Jaker788 Graphene sounds promising, kinda wonder if carbon could be added to silicon... if they could even slightly improve it's conductivity heat would drop massively.
You need to turn off your transistor. Carbon is very good turning on but bad when turning off. That is the problem. If what you want is just a good conductor then use copper.
Are we ever going to see cpu's made from diamonds? I saw a discovery/natgeo episode on TV a long time ago that talked about how diamonds can be turned into a semiconductor and that they have a very good thermal conductivity, better than copper. Since then I've never heard of it again.
Absolutely fascinating TY mate. Subbed n liked. As you bought up your youthfulness take it from an old man protect your wrist, arm, mouse-finger, and generally hand and get yourself a decent vertical mouse. It's either that or you can join the team who need their palms injected regularly. Best wishes.
At what point along this roadmap do you think that noticeable proportion of generational performance uplifts (or simply energy improvements) will come from integration of optics into the package? There are plenty of optical tech S-curves that can stack - providing improvement runway for 30+ years (at the rate we have historically demanded from the semiconductor industry). This doesn't seem to be true of our good friend the silicon FET.
You know you've always reminded me of the son of an old friend of mine who was a MENSA member and that shirt has only made it worse. He worked with Python at some point. His father had a Commodore 4000. I'm fairly certain you are not him but the resemblance is uncanny.
From what I am understanding, we are running into problems that the next EUV lithography machines from ASML and the resist materials are just running into problems getting any smaller and things like multi patterning won't help much, but will slow down wafer processing until it's currently uneconomical except for producing extremely expensive high performance chips that will not make its way into the hands of the average consumer.
Any idea on tech to help you print you own chips in your home? Sounds crazy but I think this is where we should be going and not towards the continued centralization of chip production.
Let's be honest, post silicon tech is absolute necessity to actually maintain Moore's Law to the end of this century. Packing silicon based transistors tighter is guaranteed to become exponentially more problematic and cost prohibitive over time, the laws of physics will make this an absolute certainty.
@@TechTechPotato It just needs to be good enough in a specialized application to prompt accelerator use and grow the industry from there. If something like graphene can be used to achieve Terahertz speed processors, even very basic or large feature size ones, there are a lot of high value applications that are heavily limited by purely sequential calculation. Even if it's only a couple million transistors, some of those computations don't take much, they just absolutely need to be done one right after another and can take a very long time in a typical CPU.
Most foundry events are no photos, no video, no audio, aside from like the first 10 minutes. They go through slides at a rate of about 6 per minute and trying to write anything down. It's mostly show and tell for C-level customers and investors.
Do you expect we will see non-photon-based lithography - electrolithography for example, with electrons? After all their frequency can be a lot higher than EUV, making their achievable resolution a lot better (until you go high enough that you start eroding surfaces of course…) Of course, this would require new types of resists and so on.
I wonder if the power consumption for EUV will put TSMC at a disadvantage, being an island with limited energy capability. The USA though has lots of capability so it might give Intel an advantage being the US has so much energy potential.
You can plop down a nuclear reactor capable of delivering >1GW in basically any region so I don‘t really see that being a problem. Also looking at the news, the US might have larger production capacity but their grid seems to be really really old and mismanaged with all the outages in Texas or fires in California. And obviously if Taiwan ever manages to somehow burry the hatchet with China for good, they could realize something like the Asian super grid and build grid interconnects.
Do you think future chip manufacturing could be done in space? Maybe at some point the advantage of an ultra-high vacuum, absence of gravity and general low disturbances outweighs the launch & recovery costs. Space manufacturing is certainly more useful than a Mars colony.
Look at how large a fab is - and imagine the energy it needs to run. Now look at the price to build one fab on Earth. Doesn't seem possible to build one in space with current technology besides the cost - light source needs gravity for EUV for example. In space you also have more radiation which creates it's own problems.
@@JL-pc2eh Thanks for your insight. I didn't mean to build a whole fab, just enough to build parts of a cpu which could benefit from the unique conditions. Having enough power in space is no problem. There are sun-synchronous orbits able to generate electricity 24/7 at a higher power density then anywhere on earth. The dangerous radiation from the sun is directional and can be blocked by shielding. I'm not sure if you need shielding from other directions.
Unfortunately there are tons of steps for a chip that take months to get through. An entire chip fab is a very long assembly line/pipeline that must be passed from start to finish to get 1 finished wafer. When the power goes out due to a natural disaster, the whole pipeline and months of production are lost, and it's happened before.
@@Jaker788 I had an internship at a small III-V fab right before I started grad school and about halfway through the summer, there was a power outage in the fab. Boy the engineers were not happy - plenty of ruined lots! It was mostly discrete devices on larger process sizes, but it certainly cost a ton I'm sure.
My big concern is we won't even hit A14 if Intel flops with 20A/18A and TSMC gets super complacent with their 14A not arriving until late 2027 the earliest and Apple hogs it for 2 years.
I wouldn't be so down with Apple, they are bulk buying and paying up front which helpings funds TSMC's ongoing development. They are an important anchor tenant.
CFETs are technically forksheet GAAFETs, so it's not surprising that it's not on TSMC's roadmap, so it's akin to putting all eggs in a basket before anything else.
Sorry, had to delete the EUV lithography part, RUclips kept butchering my edit. LOL Welp. And yep, X-ray spectrum is honestly not as strongly defined though. X-ray and EUV lithography is challenging, especially, unfortunately with Tin sources having efficiency problems. Making very short wavelength light is no easy task.
Still, kinda looking forward to the Silicon-free transistor future as the Dark Silicon is kinda a problem, especially with leakages of Silicon transistors.
Frankly just looking at the slide you can see the end is nigh. Can't go beyond a single atom. And even at that scale quantum effects step in already. Can't average output from the group of one. Plus every atom must be placed perfectly and not get cracked by some interstellar rogue particle sh!t. We are pretty much at the peak development right now. Enjoy it. The rest is squeezing last juice. "Computer enthusiast" may sound as niche as toaster enthusiast some day. Well done report, thumbs up.
@TechTechPotato: wouldnt be so sure about the EUV thing in your lifetime. Maybe its the last generation of masked lithography, but there is no reason that efficient ways of additive manufacturing will be found, or using directed electron-beams, which are able to scan and scale better then the current technology. There are lots of papers in the regards of additive lithography. So I bet we will see something like that in our lifetime
@@TechTechPotato Check out the G14 subreddit. u/ispeakuwunese has a guide post about getting battery life back and what he thinks they changed that broke efficiency.
well but meanwhile in the present and near future things are looking very ugly on latest stuff everything going at very high wattage that makes it look like silicon would never be the future... Really hope by 2030 we would already have computers working with light instead of common transistors.
It's interesting they have a road v map to all this if they know how to get to A2 why don't they just build the equipment now and save all the middle steps. When I see this layered approach with GAA it looks like a much more costly design. So I'm guessing that if you want any tech with scales lower than n3 you will be paying 1000-10000 a chip to manufacture. This makes sense for military applications but I don't see it happening for consumer products.
They may theoretically know how, but the process steps and hardware are not even close. This is something that'd need to be worked on as you move through the nodes before. You work your way down incrementally or you end up with another Intel 10nm disaster by trying too much at once without all the tech being ready
@@Jaker788 exactly this. Build the first of something is hard, the second and third one easy but building a million is incredibly difficult. Manufacturing anything at scale is a serious challenge, far greater than being able to produce a few GAA transistors in a lab.
@@PhilfreezeCH but I would think that lab experiment's would be devised in such a way to prove a mass production process viable. What purpose would research be if they were just studying the functions of transistors at these scales. It would be equivalent to saying they can build nano circuits at scale because they can build them in the lab. Of course in reality moving an electron microscope and ionising atoms on the target is possible to create nano circuits if you have the patients to create a transistor at a time over 20-40:hours. But I'm guessing there research is focused on mass produced designs not lab experiements. Of course it is easier to go from A-C than A-Z but if they is the final target then why not just work it out before stating it is possible but unfortunately I think these kind of discussion are just academic and don't have viable solutions they talk about A-Z but have no idea how to do B, C, D... Steps.
@@justindressler5992 Because we may not know if it even works I guess. IBM has done one off stuff before like 3nm transistors and smaller, but we didn't have the equipment like EUV to actually mass produce wafers or circuits. Here's an example. Intel tried to skip a gen with 10nm essentially, this was starting in around 2014, the proposed density was more than TSMC 7nm. They replaced FinFET with contact over gate, very compact, however the tolerances were extreme and yields were horrible. They did this without EUV because it wasn't ready. They replaced copper with cobalt because it had less leakage and required less insulation, however it's thermally brittle. The chips that did come out were horrible on almost every metric except density. Intel 10nm eventually went back to FinFET, dropped the pure cobalt traces, and went much less dense. Intel is only just now using 10nm and it's completely different that proposed originally. Meanwhile TSMC and Samsung took steps along the way and incrementally learned and developed their process instead of leaping. They're ahead of Intel when previously they were a decent margin behind Intel. Contact over gate is abandoned currently, and gate all around is what will replace FinFET. Similarly Jim Keller has talked about architecture design. When a new microarchitecture is made they quite often leave "low hanging fruit" to be improved in the next gen, like widening decode, making things bigger, adding an op cache. If they kept working on that generation and didn't leave stuff to be improved, they'd spend a ton of time, possibly more than if left to fix later. Now that team can move on and add even more on the next major architecture 5 years down the road, and the other leapfrog team can make the improvements for the next upcoming gen often a bit in parallel once enough if sketched out. There's 3 leapfrogging teams at AMD for CPU architecture. TSMC also uses leapfrogging teams for lithography.
@@Jaker788 yep this is my point the graphic presentation of a road map to the future has nothing to do with the reality if they truly had a working plan they would just implement it. It's a little like watching Space X CGI presentation of man colonizing Mars. There are far more unknowns than certainties to make it happen. I think the real direction forward now for the chip industry is multiple low cost CPU and GPU on PCB design. The Chiplet style design like AMD can only go so far from a thermal/performance point of view and scaling is just not viable anymore. Just look at the best chips in the industry such as Apple, Samsung at 5nm they retail at almost three times the price from previous generation. Could this be greed alone or is there significant cost increase to produce these 5nm parts. It would be far cheaper to produce 10 or even 12nm hi yield parts and place two on board. Of course mobile low power devices need density to scale but I think we won't see any major improvement here for at least another 10 years. At this point only minor incremtal changes and mostly targeted at reducing cost by improving yield.
It was my machine growing up. I'd write the BASIC programs out from the C64 magazines I'd get every month. Bubble Bobble on tape took 7 minutes to load.
It's pronounced Ongstrum, with it being spelled ångström and all. Swedish name. Should have just been in picometers. What's wrong with P1400, P900, etc.
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I think the “what’s next beyond EUV” question deserves a video. The generation and manipulation of photons past EUV becomes a big issue.
After EUV (soft x-rays) we move to hard x-rays right? That's probably going to be hard to control.
@@Jaker788 Do we need to stick with photons? I realise they have a lot of nice properties but they aren’t the only particles one can use
@@mduckernz I'd think hard x-rays are hard enough to focus and control exposure. Maybe taking a page out of cancer radiotherapy, a linear accelerator that can accelerate x-rays, electrons, or protons in a focused manner is a possibility. I'm not sure how those particles work for photolithography, maybe new resists needs to be invented and modification of the LINAC machine.
I know there are some alternative machines not used that instead of using a large mask and exposing the whole wafer at once, work more like a CNC. Very slow but I think it was more accurate and precise? Maybe a LINAC could be focused to directly draw the design without a mask, probably extremely difficult, I don't know what's required to do that kind of precision and how the CNC type lithography machines work to begin with.
@@mduckernz Electron Beam Lithography is very interesting and can take us down to the atomic level. Look it up on Wikipedia. The only problem with EBL is that it's terribly slow, so slow that it is completely uneconomical unless someone can speed it up dramatically somehow. (Multiple beams is one idea that they are exploring.)
@@PremierSullivan Indeed, electrolithography (? Not sure if that’s a valid name for it, but you get the idea…) was the main approach that seemed viable to me.
Multiple beams sounds very doable, you just need to make sure they don’t pass too close to each other so they won’t repel each other and deflect their beams.
I also wonder whether you can do away with the beams, and instead use a modified resist and mask, and then bathe the silicon in electrons, treating them as if they were light.
The beams approach seems likely to work, and be effective, but yeah as with you I worry about the speed of it.
I'm hearing a lot about increases in transistor density, but I have a sneaking suspicion that raw improvements in power efficiency will become more elusive over time, leading to greater considerations of things like the Landauer Limit, for instance, or in other words, leading to advanced nodes that pack tons of transistors clocked lower than current nodes, in order to avoid excessive thermal stress...Possibly leading to a revolution in software as we adjust our workloads for wider compute chips with massive parallelization capabilities, a good example of which is the rapid increase in AI based accelerators.
i'm actually not sure if that's really going to happen. power generation is ramping up exponentially with compute demand. datacenters don't seem to be more concern about power bills as much as they are concerned about squeezing the most compute possible. which means more power, as expensive as it is, is still cheaper than more compute.
GPUs are getting more power hungry primarily due to exploding compute demands, and the benefits are justifying the higher power bill.
My understanding is transistor density increase usually leads to power efficiencies improvement's however they can choose to focus on more performance or more energy savings
@@kicapanmanis1060 maybe, but from what i can see this is really been driven over the last 5 or so years by an explosive demand of AI compute that just keeps skyrocketing, which is mainly done on GPUs. this would explain why GPU power consumption has taken over CPU by such a large margin.
I think at some point near threshold computing may be necessary
bro the wide revolution has already been underway for a decade
Newsletter version: morethanmoore.substack.com/p/imecs-roadmap-to-2d-transistors-in
[00:00] Teaching Rocks How To Think
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[01:05] Who are imec?
[02:35] imec Technology Forum
[03:17] 2018: N7, Metal Pitch, Tracks
[04:25] 2020: N5
[04:36] 2022: N3
[04:50] 2024: N2 and Gate-All-Around
[05:09] 2026: A14
[06:00] 2028: A10 and Forksheets
[06:36] 2030: A7
[06:49] 2032: A5 and CFETs
[08:08] 2034: A3
[08:16] 2036: A2 and 2D Transistors
[09:17] Other Roadmaps and VTFETs
[10:04] Paper on 1nm, or not
[10:46] Backside Power Delivery and Packaging?
[11:20] Beyond EUV?
[12:23] Cat Tax
That Commodore shirt is killing it! 😎
Exciting! The amount of manpower to make chip fabrication possible is baffling. The type of structures for different nodes is also super exciting and I want to watch more about it.
Ian, fantastic tutorial on the direction of advanced node development. I’m sharing this with my team.
Thanks Kim! Feel free to reach out if ever you're looking for sponsored content. A deeper look into the future of EDA in a chiplet and stacked world would likely go over very well
I think the real technology breakthrough would be teaching devs to stop reinventing wheels that need 10x the compute to do the same things we already could do.
Thanks Doc!!! But don't forget:
PHOTONICS ARE THE FUTURE!!!!! :D
Thank you Dr. Ian Cutress for bringing to Technologists minded people the latest and future updates,
with such an informative but at the same time focused on essentials, manner.
For reminding me , your outro track and cat's playfulness,
a little something from a fellow countryman of yours .:
Squarepusher (Tom Jenkinson) - Angel Integer
This is one of the best tech presentations I have ever seen on RUclips. Tech TechPotato a huge thumbs up.
this review was awesome, it's like a breeze of fresh air compared to other over-simplistic channels. congrats
Thanks Ian for this. I know it might appear that EUV maybe seem like the end of the road, we may yet find a way to move the path of X-rays.
It also been wonderful seeing you hanging out with Wendell, Steve, Gordon etc. I know I'm not the only person who likes that tech youtubers are a community not a competition.
I see the same thing happening in the Guitar/amps/pedal/mic/music/production space with a lot of them meeting up at #42gsthree & #42gsfour
And all having that awful "carpet" in the background... :)
If EUV was being discussed about in the 80's, and its mass usage is in 2022, what technologies and scientifical concepts are being discussed today, apart from the one layer of atoms? If you know, that is ofcourse. I would like to imagine what they will do 50+ years from now
Artificial general intelligence. When computers can think better than humans and much faster, all bets are off. We could get a century of progress in a few years.
There is nothing beyond EUV. There is an upgrade the High NA EUV. Prototype machine are already being built but it would take a couple of years before it enters mass production. After that the industry would have to rely on multi patterning to keep scaling. This is of course the lithography side. The transistor side have a lot more avenue for squeezing density. And there is also the packaging side where a lot of research is going into increasing chip density.
Getting current into and out of dissimilar materials can be a real issue (without large voltage drops). Glad they're getting a start on it now! 😃
I know silicon carbide is only used for power Mosfets, but you can do crazy high clock speeds with this stuff. Maybe in 50 years we might see some VLSI SiC chips, then with fabrics, assemble liitle SiC chiplets into fast little CPU's? Or not.
Super good analysis and inshowcasing what the major players are doing in this space. What would be interesting is if a review / analysis can be done of what these major fab players are doing in terms of building facilities, identifying the products they will be making, when and where (globally speaking) -- in light of the recent geopolitical turmoil, the US CHIPS act, etc.
If you wonder: there's an alternative to EUV lithography: EBL lithography (electron beam lithography). It already exists today & actually allows even smaller features than EUV, for example it already managed to produce single-atom wide features about a decade, but it does also have drawbacks: all research work I've come across indicates that it's difficult to use for mass production because results are difficult to reproduce & also costs, which is why commercial semi fabs don't use them (yet?) but some research labs do. I know some companies are trying to commercialize that but with an unknown amount of success.
Dosent the Eldctron beam expose each layer like a televison tube writing each frame onto the screen instead of in one single burst with EUV-litho?
Will it make very advanced IC manufacturers alike Pharaohs? So far away from common people, they will appear like gods. So much power over everyone.
The Taiwan government representative is a member of the board of directors of TSMC, and the Taiwan government will never let TSMC be completely out of government control.
@@TriNguyen-he7xk I don't understand.
It's already very much like that in every field. Billionaires are so far removed from you and I, yet wield enormous influence over both their own industries as well as govt policy. These aliens are dictating huge swathes of our lives, not least limited to the majority of our time that we spend working to make them more money.
Worry not about the semiconductor foundries, they are staffed by ordinary people trying to work for a living like you and I. Worry more about the billionaires exploiting their labour and destroying the planet with overproduction, and the legions of other owners that amplify and venerate the billionaires.
@@TriNguyen-he7xk Pharaoh lives matter
@@TriNguyen-he7xk 😆😆🙉🙉
Extremely interesting video. I wonder if there isn’t there more literature on the subject of scaling, metal-tracks and metal-pitch (that isn’t impossible to understand for average readers).
As long as you can get access to the papers, I’d recommend just try to read a few, you pick things up through context clues pretty quickly (keeping notes of the acronyms on the side can also help). Also, review papers and the literature review sections of thesis papers tend to be quite comprehensive and can be a good place to start when looking at a new topic
"Forksheet GAAFET" is a terrible name, they should have called them "ForkFETs"
What's next, SporkFET?
Forklift CertiFET
@@NarekAvetisyan
Before I Forget 🤟
The ending was absolutely brutal :)
I'm predicting that fabs will have to switch to some other semi materials as Si for the channel long before the A2, somewhere between A5 - A10.
when you look at these road maps, and think what is in research vs what we get from year to year, it becomes mind boggling... that last statement was really depressing, but who knows maybe new euv technology is not the future, they might ditch it in 10 - 20 y
EUV has been a 35 year journey. Going beyond EUV has to have started today, and will take 35yr+. As far as I can tell, very little work is being done beyond EUV. High-NA sure, but that's mirrors, not sources.
@@TechTechPotato crazy ideas come every year, we can never know what the future holds. How Is the quantum computer working?
@@TechTechPotato but are there none competing processes in the works, that just have not matured yet? 🤔😲
There are small time research with alternatives. But there is no industry wide push to develop a technology beyond EUV. Without Industry wide coordinated effort to make something happen nothing will happen. The cost to develop something better than EUV is just to high that no single company can afford it. It has to be a team effort by everyone and even with everyone involve it will take several decades.
0.2nm is less than the diameter of a silicon atom. Sure you have to hit the quantum tunnel limit at some point before that :D
Good thing it's only a NAME, and not an actual physical dimension. It's meant to represent a theoretical planar transistor.
@@TechTechPotato I know, and that's like selling a 60kWh capacity car battery under the name "600kWh". And then imagine different manufacturers slapping random kWh numbers on their batteries to try to outcompete each other.
Misusing physical quantities with a well defined meaning as marketing names is beyond misleading.
Another such example that comes to mind is "resolution" of video projectors. Manufacturers market them as "4K", but it's actually just maximum supported input signal resolution and the projector then can only do a 720p image on the wall. The "native resolution" is hidden in small print.
@@ProjectPhysX Meh, it's representing the increase in density over a number of factors. Actual transistors size is just one of a handful such as, total gate area from design changes to GAA and such, space between gates, etc. You really can't just slap an accurate number anymore to actually represent the size so I'm not sure what you'd want.
@@Jaker788 of course you can put a precise number on it, and there is proposed standards to do so via transistor density. For example, count the number of transistors per mm², then calculate the average square transistor side length.
@@ProjectPhysX So you've got density down, but not quite. You have High performance cell libraries that are going to be less dense but handle more power, and there are at least a few cell libraries to choose from, all with different density and other specs. You've got ultra dense cell libraries for SRAM, stuff for logic, efficiency, custom ones for specific large customers. So even within a node there is no set density per area. There's leakage, power capability/density, efficiency, switching speed, doping materials, etc. There's a lot to a node that you just can't represent accurately.
There's so much to a process node. The current naming shows up a relative improvement over the last though, and that's pretty good without making a specific claim to density. For more specific specs you can look into their datasheet and get as much info as they're willing to show the public, which isn't everything and every cell library.
On a side note about EUV, I'm surprised they are using CO2 lasers, instead of diode or fiber ones. I guess it keeps the large capacitor manufacturers in business!
The A10 process node in 2028 will be a good time to buy/build a new computer.
Great video!
Everyone in RUclips : "let's get a good catchphrase for the end of our videos"
Dr. Ian: "hold my beer"
having writing deep dive tech articles on anandtech to making deep dive tech videos, you rocks.
Check my newsletter - www.more-moore.com
this is some great content. learned a lot. ty for the video
At this point I would really like to know what the maximum theoretically possible density limit for transistors would be.
And with "maximum theoretically possible" I mean the limit where the laws of physics say stop, not where it stops being economically viable to do because of small yield and production cost.
I think there was some experiments involving a single molecule transistor, where (as the name says) where a single molecule reliably was able to work as a switch. I think the main problem is gonna be how do we putt a lot of these in a small space and how do we make it affordable. I think the future will be a combination of different technologys like nand flash based neural networks and conventional silicon with big simulation tasks being done by quantum computers in big data centers.
We will reach a point where instead of going smaller, we start building smarter transistors.
A bunch of binary transistors can do some work. But take a transistor and make it do more than 2 states?
That's where the big progress will come.
Neuron like computers that can dynamically adapt to different jobs, plus being able to remember information on the Neuron itself.
@@jakobmax3299 two question:
1. what was the molecule
2. how big was the molecule
don't forget, he mentioned atom-sized sheets here
@@ghoulbuster1 quantum computers are similar to what you are describing
@@kuhluhOG I dont remember, but thats not even the point. Transirors as we know the have a size minimum, and at some point we have to make the choice between affordable chips and the most powerfull chips.
Don't let Jim Keller watch the last segment! 😁
Will EUV suffice for the next 40-50 years at the pace we're going though ? And what tech could replace it (at least in lab conditions) ?
All the tricks we've used pre-EUV we can apply to EUV, but they'll run out by the end of the decade probably.
@@TechTechPotato You say that EUV wont get replaced in your lifetime, in all probability, but I posit to you that with advancements in quantum computing and AI, there will be problem solving of thousands of years of all the worlds super computers of today, done in a few hours. Quantum Computers are not really useful right now, for the most part, as I understand it, but that is set to likely change starting in a couple of years. A.I. achieved, with the AI that won at GO, what was thought to be 10 years ahead of schedule at that time. And AI researchers don't even fully understand what it going on, that's how crazy its already getting.
Hopefully it doesn't end in disaster, but the advancements in intelligence itself would seem to be the thing that will allow us to go past EUV lithography, and doing so by the 2040s I'd guess.
It seems the thermal regulation of CPUs and GPUs is becoming more and more restrictive and it was suggested somewhere that it was a hinderance to AMD's 3D vcache chips.
Is there any kind of microtubule type technology on the horizon that would allow water or equivalent coolant to actually flow through the meat of the die, potentially allowing them to stack more and more layers without the problem of overheating?
In microtubes there would be the limit of the possible pumping volume of the coolant and the high purity needed.
Another problem would be the expansion of the coolant in high temperatures by making the chip silicone go skadoosh 💥
😂
im guessing theres good reasons why they wont be using graphene.. And im wondering if Molybdenum disulfide is a type of graphene because its a 2D layer?? another thing i thought intel once mentioned was carbon nanotubes or nanowires but i dont think its mentioned here.
In layman’s terms - we are not limited for space or power except in mobile or avionics so is the forcing function of the roadmaps - higher density and faster speed with lower power for mobile phones and weight/ space constrained applications plus perhaps cloud based servers who’s input cost has a large power component ? Whilst the shrinkage and chemistry and manufacturing tolerances are impressive , is the software keeping up ? . An 8k video from an iPhone just means that you need an 8k monitor , 8 k edit suite , 8 k graphics card , more memory , faster motherboard , more SSd storage - for what ? Many years ago Nicholas Negroponte from MIT media lab said “ we are spending vast resources developing high bandwidth interconnect networks , but hardly any on what we put in one end , and how we interpret the output “ . The old garbage in garbage out story .
Would be great if you could talk about SiC and GaN and for good measure may be even throwing in GaAs, which was long time the contender for replacing Si/SOI
What a beautiful laptop you have! As for aesthetics, I like the choice.
How can they continue to reduce cell height (given in metal tracks not physical) without increasing width though?
Isn‘t that just a geometry problem at some point?
I mean one obvious thing is buried power which frees up a good amount of cell height, apart from that though, are they planning to use more metal layers for cell-level tracks or what?
Moving to Nanosheet allows for reduction for cell height because the fins are now sideways and you can just adjust channel width to reduce the cell height. Forksheet inprove this because the N channel and P channel are now side by side separated only by a barrier so two transistor are squeeze into a width of 1.5 transistor.
Hope we all start using transistor density metrics soon
Perhaps divided by power consumption or something. Too many unknowns still 🤓🙃
Also: if actual channel width gets below 5A then they really have to switch from FETs to tunneling transistors because no material or design can prevent tunneling through the channel at this scale.
Not necessarily. You put more insulator around the wires, you get less tunneling. Lower voltage, less tunneling. Lower temperature, less tunneling. Etc.
@@Anenome5 I was talking about channel width, not insulation around wires. OTOH yes, one can also try to improve channel insulation, but that has already been done A LOT & I fear there won't be any space or way left to add sufficiently more insulation around channels to prevent decrease in channel off-resistance due to tunneling of charges/holes to such a point that field effect transistors can't be used as proper logic switches anymore so that engineers will have to embrace tunneling effect by using tunneling transistors & ditch field effect transistors entirely.
What mouse are you using mate? Great video as usual. Thanks!
MX Master
@@TechTechPotato thanks man, looks comfortable
Why aren't they moving to a new semi-conductor earlier?
Density notwithstanding, a lower switching voltage would benefit everything, could possibly double clock speeds and halve power usage at the same time.
TSMC has started researching alternative materials. I'm guessing this will materialize as new doping materials first and some R&D into manufacturing these alternative wafers, doping materials to create a band gap if needed, how to do lithography, and characteristics.
We've as a whole been researching alternatives for a while now. The hard part is finding one that is a decent semiconductor, or how to make something that's not a semiconductor actually be one with good characteristics.
@@Jaker788 Graphene sounds promising, kinda wonder if carbon could be added to silicon... if they could even slightly improve it's conductivity heat would drop massively.
@@glenwaldrop8166 The main problem is how to turn a superconductor into a semiconductor. They haven't found a good doping material yet for graphene
You need to turn off your transistor. Carbon is very good turning on but bad when turning off. That is the problem. If what you want is just a good conductor then use copper.
@@kazedcat You're ignoring half of my comment.
The switching voltage needs to be lower, hence adding a conductive material to the silicon.
Thank you Ian.
So in 2023 is the best time to upgrade from intel dual core ? Or in 2024
Are we ever going to see cpu's made from diamonds? I saw a discovery/natgeo episode on TV a long time ago that talked about how diamonds can be turned into a semiconductor and that they have a very good thermal conductivity, better than copper. Since then I've never heard of it again.
Unlikely. I never see any research on it at the conferences I go to
Isn't the effective field of an electron 1nm?
That would mean that no matter how small the circuit is we need a 1nm gap, ultimately limiting density.
The process node is a name, not an actual dimension. :)
@@TechTechPotato yeah, I posted the question before I finished the video...
lol
Absolutely fascinating TY mate. Subbed n liked.
As you bought up your youthfulness take it from an old man protect your wrist, arm, mouse-finger, and generally hand and get yourself a decent vertical mouse. It's either that or you can join the team who need their palms injected regularly. Best wishes.
At what point along this roadmap do you think that noticeable proportion of generational performance uplifts (or simply energy improvements) will come from integration of optics into the package? There are plenty of optical tech S-curves that can stack - providing improvement runway for 30+ years (at the rate we have historically demanded from the semiconductor industry). This doesn't seem to be true of our good friend the silicon FET.
Optics looks good for data transport, not so much for compute. Density could be a real issue there.
EUV should get us to the Singularity then the AIs will get us beyond it.
Come for the tech, stay for the kitties.
Is there research into other geometries or are the creation of transistors the only goal?
explains a lot! thank you!
You know you've always reminded me of the son of an old friend of mine who was a MENSA member and that shirt has only made it worse.
He worked with Python at some point.
His father had a Commodore 4000.
I'm fairly certain you are not him but the resemblance is uncanny.
Where does Graphene come in? The EU invested a lot and built half a campus for graphene semiconductors at a nearby university
From what I am understanding, we are running into problems that the next EUV lithography machines from ASML and the resist materials are just running into problems getting any smaller and things like multi patterning won't help much, but will slow down wafer processing until it's currently uneconomical except for producing extremely expensive high performance chips that will not make its way into the hands of the average consumer.
I think that's what he meant when he said photolithography won't progress past euv in his lifetime (if ever)
Any idea on tech to help you print you own chips in your home? Sounds crazy but I think this is where we should be going and not towards the continued centralization of chip production.
Check out Sam Zeloof. He's doing that sort of thing
@@TechTechPotato I have been tracking his progress for a while now. I was talking more about companies creating machines and the such.
Let's be honest, post silicon tech is absolute necessity to actually maintain Moore's Law to the end of this century. Packing silicon based transistors tighter is guaranteed to become exponentially more problematic and cost prohibitive over time, the laws of physics will make this an absolute certainty.
Anything that comes along will have to compete against 50+ years and trillions of dollars of innovation on day one.
@@TechTechPotato It just needs to be good enough in a specialized application to prompt accelerator use and grow the industry from there. If something like graphene can be used to achieve Terahertz speed processors, even very basic or large feature size ones, there are a lot of high value applications that are heavily limited by purely sequential calculation. Even if it's only a couple million transistors, some of those computations don't take much, they just absolutely need to be done one right after another and can take a very long time in a typical CPU.
We need to improve the EUV light source to improve production speed moving to SSMB steady state micro bunching
Can you make a video to explain how does a modern IC works
I think there will be improvements on EUV specially on the cost side. I think some completely new design thinking will come around 2032 mark.
Really dumb question. Why would TSMC share the roadmap with you but not allow it publicly ? Is you're doing consulting for them or something else ?
Most foundry events are no photos, no video, no audio, aside from like the first 10 minutes. They go through slides at a rate of about 6 per minute and trying to write anything down. It's mostly show and tell for C-level customers and investors.
@@TechTechPotato Thank you
I'm 30 now so by the time I'm 40 will this make zen 10 and rtx 9090 perf inconceivable?
An Epic T-shirt man.
It's 2024 and I'm actually wearing a device with a 3nm GAA transistor chip rn.
And the van der waaals atomic radius of silicon is about 0.22 m. That would be the ultimate wall. Check it at wikipedia.
Or, check it at wikipedia that node names are NAMES, not distances.
@@TechTechPotato That's clear but you can count atoms right now and thats the natural border to quantum weirdness !
Great video, thanks!
Do you expect we will see non-photon-based lithography - electrolithography for example, with electrons?
After all their frequency can be a lot higher than EUV, making their achievable resolution a lot better (until you go high enough that you start eroding surfaces of course…)
Of course, this would require new types of resists and so on.
Any news in graphene?
It is still bad turning off.
@@kazedcat yes, but rotated Graphene solved that problem
@@Dahs312 So you rotate graphene to turn it off. How fast can you rotate graphene to do this. Mechanical switch is very slow.
I understood... pretty much nothing. I don't understand how different MOSFET configurations actually are built and work.
Beyond EUV we will need to put on our big boy pants and use electron lithography to make ASICs :P
100000 dollar i3 LETS GOOOO!!!
They just need to work backwards, plan out how to make them stupidly small and then upscale until reasonable yeild
Nice metal mask behind you
Where is the Optical bus? Where is the electrin spin circuit
I wonder if the power consumption for EUV will put TSMC at a disadvantage, being an island with limited energy capability. The USA though has lots of capability so it might give Intel an advantage being the US has so much energy potential.
You can plop down a nuclear reactor capable of delivering >1GW in basically any region so I don‘t really see that being a problem.
Also looking at the news, the US might have larger production capacity but their grid seems to be really really old and mismanaged with all the outages in Texas or fires in California.
And obviously if Taiwan ever manages to somehow burry the hatchet with China for good, they could realize something like the Asian super grid and build grid interconnects.
I wait for the GAGA transistor. No matter what hardware improves, silly software features consume the progress
When will ebeam lithography take off? Seems like a no brainer to me.
Do you think future chip manufacturing could be done in space? Maybe at some point the advantage of an ultra-high vacuum, absence of gravity and general low disturbances outweighs the launch & recovery costs. Space manufacturing is certainly more useful than a Mars colony.
Look at how large a fab is - and imagine the energy it needs to run. Now look at the price to build one fab on Earth.
Doesn't seem possible to build one in space with current technology besides the cost - light source needs gravity for EUV for example.
In space you also have more radiation which creates it's own problems.
Light based computing could benefit from space manufacturing because cristals grown in space have less defects.
@@JL-pc2eh Thanks for your insight. I didn't mean to build a whole fab, just enough to build parts of a cpu which could benefit from the unique conditions. Having enough power in space is no problem. There are sun-synchronous orbits able to generate electricity 24/7 at a higher power density then anywhere on earth. The dangerous radiation from the sun is directional and can be blocked by shielding. I'm not sure if you need shielding from other directions.
Unfortunately there are tons of steps for a chip that take months to get through. An entire chip fab is a very long assembly line/pipeline that must be passed from start to finish to get 1 finished wafer. When the power goes out due to a natural disaster, the whole pipeline and months of production are lost, and it's happened before.
@@Jaker788 I had an internship at a small III-V fab right before I started grad school and about halfway through the summer, there was a power outage in the fab. Boy the engineers were not happy - plenty of ruined lots! It was mostly discrete devices on larger process sizes, but it certainly cost a ton I'm sure.
My big concern is we won't even hit A14 if Intel flops with 20A/18A and TSMC gets super complacent with their 14A not arriving until late 2027 the earliest and Apple hogs it for 2 years.
I wouldn't be so down with Apple, they are bulk buying and paying up front which helpings funds TSMC's ongoing development. They are an important anchor tenant.
CFETs are technically forksheet GAAFETs, so it's not surprising that it's not on TSMC's roadmap, so it's akin to putting all eggs in a basket before anything else.
EUV used to be called Soft X-Ray in the 80s.
Sorry, had to delete the EUV lithography part, RUclips kept butchering my edit. LOL Welp. And yep, X-ray spectrum is honestly not as strongly defined though. X-ray and EUV lithography is challenging, especially, unfortunately with Tin sources having efficiency problems. Making very short wavelength light is no easy task.
Still, kinda looking forward to the Silicon-free transistor future as the Dark Silicon is kinda a problem, especially with leakages of Silicon transistors.
Smoke in the air! - Smoke in the air!
Frankly just looking at the slide you can see the end is nigh. Can't go beyond a single atom. And even at that scale quantum effects step in already. Can't average output from the group of one. Plus every atom must be placed perfectly and not get cracked by some interstellar rogue particle sh!t.
We are pretty much at the peak development right now. Enjoy it. The rest is squeezing last juice. "Computer enthusiast" may sound as niche as toaster enthusiast some day.
Well done report, thumbs up.
This is super interesting stuff.
Yes. We fired electron bolts at a sand and taught it how to think. Humans is too advanced.
@TechTechPotato: wouldnt be so sure about the EUV thing in your lifetime. Maybe its the last generation of masked lithography, but there is no reason that efficient ways of additive manufacturing will be found, or using directed electron-beams, which are able to scan and scale better then the current technology. There are lots of papers in the regards of additive lithography. So I bet we will see something like that in our lifetime
Nice G14! How are you enjoying BIOS 313 lol
The low power mode doesn't like low power!
@@TechTechPotato Check out the G14 subreddit. u/ispeakuwunese has a guide post about getting battery life back and what he thinks they changed that broke efficiency.
２００ピコということですね。１０ピコはこれから先行けると思われます。ガンバレー！
What ever happened to graphine as a material?
well but meanwhile in the present and near future things are looking very ugly on latest stuff everything going at very high wattage that makes it look like silicon would never be the future...
Really hope by 2030 we would already have computers working with light instead of common transistors.
2D transistors are based on MXenes ?
you left the ND filter off the camera :p
I thought IBM does research into novel processor tech?
It's interesting they have a road v map to all this if they know how to get to A2 why don't they just build the equipment now and save all the middle steps. When I see this layered approach with GAA it looks like a much more costly design. So I'm guessing that if you want any tech with scales lower than n3 you will be paying 1000-10000 a chip to manufacture. This makes sense for military applications but I don't see it happening for consumer products.
They may theoretically know how, but the process steps and hardware are not even close. This is something that'd need to be worked on as you move through the nodes before. You work your way down incrementally or you end up with another Intel 10nm disaster by trying too much at once without all the tech being ready
@@Jaker788 exactly this. Build the first of something is hard, the second and third one easy but building a million is incredibly difficult. Manufacturing anything at scale is a serious challenge, far greater than being able to produce a few GAA transistors in a lab.
@@PhilfreezeCH but I would think that lab experiment's would be devised in such a way to prove a mass production process viable. What purpose would research be if they were just studying the functions of transistors at these scales. It would be equivalent to saying they can build nano circuits at scale because they can build them in the lab. Of course in reality moving an electron microscope and ionising atoms on the target is possible to create nano circuits if you have the patients to create a transistor at a time over 20-40:hours. But I'm guessing there research is focused on mass produced designs not lab experiements. Of course it is easier to go from A-C than A-Z but if they is the final target then why not just work it out before stating it is possible but unfortunately I think these kind of discussion are just academic and don't have viable solutions they talk about A-Z but have no idea how to do B, C, D... Steps.
@@justindressler5992 Because we may not know if it even works I guess. IBM has done one off stuff before like 3nm transistors and smaller, but we didn't have the equipment like EUV to actually mass produce wafers or circuits.
Here's an example. Intel tried to skip a gen with 10nm essentially, this was starting in around 2014, the proposed density was more than TSMC 7nm. They replaced FinFET with contact over gate, very compact, however the tolerances were extreme and yields were horrible. They did this without EUV because it wasn't ready. They replaced copper with cobalt because it had less leakage and required less insulation, however it's thermally brittle. The chips that did come out were horrible on almost every metric except density. Intel 10nm eventually went back to FinFET, dropped the pure cobalt traces, and went much less dense. Intel is only just now using 10nm and it's completely different that proposed originally.
Meanwhile TSMC and Samsung took steps along the way and incrementally learned and developed their process instead of leaping. They're ahead of Intel when previously they were a decent margin behind Intel. Contact over gate is abandoned currently, and gate all around is what will replace FinFET.
Similarly Jim Keller has talked about architecture design. When a new microarchitecture is made they quite often leave "low hanging fruit" to be improved in the next gen, like widening decode, making things bigger, adding an op cache. If they kept working on that generation and didn't leave stuff to be improved, they'd spend a ton of time, possibly more than if left to fix later. Now that team can move on and add even more on the next major architecture 5 years down the road, and the other leapfrog team can make the improvements for the next upcoming gen often a bit in parallel once enough if sketched out. There's 3 leapfrogging teams at AMD for CPU architecture. TSMC also uses leapfrogging teams for lithography.
@@Jaker788 yep this is my point the graphic presentation of a road map to the future has nothing to do with the reality if they truly had a working plan they would just implement it. It's a little like watching Space X CGI presentation of man colonizing Mars. There are far more unknowns than certainties to make it happen. I think the real direction forward now for the chip industry is multiple low cost CPU and GPU on PCB design. The Chiplet style design like AMD can only go so far from a thermal/performance point of view and scaling is just not viable anymore. Just look at the best chips in the industry such as Apple, Samsung at 5nm they retail at almost three times the price from previous generation. Could this be greed alone or is there significant cost increase to produce these 5nm parts. It would be far cheaper to produce 10 or even 12nm hi yield parts and place two on board. Of course mobile low power devices need density to scale but I think we won't see any major improvement here for at least another 10 years. At this point only minor incremtal changes and mostly targeted at reducing cost by improving yield.
How small can we realistically go until we hit a complete roadblock?
It depends on the wave function of the electron.......but realistically they have a long way to go before they get to planck dimensions....
I really cannot see there being anything beyond 2d materials in the mid 30s or maybe early 40s surely has to be it. Where else can it go?
There's single molecule transistors, however you need them to offer comparable power and perf. Then it's all about stacking and power density
I have exact same mouse. It's pretty good
Same background as Gamers Nexus. #SHARINGAHOTELROOM
We tried to top and tail, but AMD insisted we had our own rooms.
@@TechTechPotato brilliant
While I love the shirt, I'm skeptical that you are old enough to remember the C64.
It was my machine growing up. I'd write the BASIC programs out from the C64 magazines I'd get every month. Bubble Bobble on tape took 7 minutes to load.
It's pronounced Ongstrum, with it being spelled ångström and all. Swedish name. Should have just been in picometers. What's wrong with P1400, P900, etc.
Clockspeeds are going to suffer node over node going forward.