You're not just a lecturer but a teacher and a good one. spending 40mins watching and critically noting down points is worth it and by far more than the 72 hours i spent on the chapter in class.. thank you so much.
I wish you were my prof. When my IC design prof is lecturing, I can't even tell if he's speaking English, but after watching your videos, everything just makes sense. Thank you so much for these videos.
If you ever had a chance to get interviewed by Apple related IC design position, you would be regret for not coming here earlier, thanks for the lecture, prof!!!
Prof, please allow me to add some memo here to explain why there is 2 on PUN and 3 on PDN: To equal PUN and PDN drive strength, assume the both network resistance: PUN-R = PDN-R = R, and we know for each transistor in PUN, it is generalized with 2R/K and for PDN, it is R/K So, for PUN-R: 1* (2R/K) = R, K = 2 For PDN-R: 3* (R/K) = R, K= 3 That is why PUN has 2C on both drain and source of each transistor and PDN has 3C on each…
Hello, I am confused because in the system I want to analyse, all of my FETs are in the velocity saturation region and they can be more easily represented by a current source than a resistor. Can anyone point me in the right direction as to how to approach this? Thank you for the video Patrick Mercier.
At 9:10 you said that the worst case scenario would be to calculate 1 one transistor turns on (the other 2 are switched off ) but in pull-down network you calculated all of them switched ON. This is a mistake therefore making the rest solution false.
at the start, why you say that in the pmos net we've 2C? I understand that in the N net you need that 3C because of R/3 and you have 3 so you obtain R. But shouldn't you have to put 1C , because the worst scenario is R in the pmos net?
For the PMOS to have same strength as NMOS, its width must be twice. That's why 2. You may look all values as multiple of some width W. Say 3W would be the width for each NMOS and 2W for PMOS.
How is it that everyone is showing the same 3 input NAND example Elmore Delay? Has no one in the history of the internet and text book figured out how to do do the Elmore Delay for a 3 input NOR gate? Sad reflection of educators for the EE field.
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You're not just a lecturer but a teacher and a good one. spending 40mins watching and critically noting down points is worth it and by far more than the 72 hours i spent on the chapter in class.. thank you so much.
for real???
I wish you were my prof. When my IC design prof is lecturing, I can't even tell if he's speaking English, but after watching your videos, everything just makes sense. Thank you so much for these videos.
University is showing itself to be a joke compared to the internet. I would gladly take an internet connection then university education any day,
If you ever had a chance to get interviewed by Apple related IC design position, you would be regret for not coming here earlier, thanks for the lecture, prof!!!
Prof, please allow me to add some memo here to explain why there is 2 on PUN and 3 on PDN:
To equal PUN and PDN drive strength, assume the both network resistance:
PUN-R = PDN-R = R,
and we know for each transistor in PUN, it is generalized with 2R/K and for PDN, it is R/K
So, for PUN-R:
1* (2R/K) = R, K = 2
For PDN-R:
3* (R/K) = R, K= 3
That is why PUN has 2C on both drain and source of each transistor and PDN has 3C on each…
@@WonderingSoccer sir what happens if we take k = 4 for nmos. Because it so confusing. Please answer
Hello, I am confused because in the system I want to analyse, all of my FETs are in the velocity saturation region and they can be more easily represented by a current source than a resistor. Can anyone point me in the right direction as to how to approach this? Thank you for the video Patrick Mercier.
At @12:00 why did we not keep the 3 parallel resistance R from the previous Pull up Network
Because for a falling edge delay the pMOS transistors would be disconnected (but the 2C capacitances would still be connected to Vout)
You are my exam saviour
Thanks a lot
At 9:10 you said that the worst case scenario would be to calculate 1 one transistor turns on (the other 2 are switched off ) but in pull-down network you calculated all of them switched ON. This is a mistake therefore making the rest solution false.
CMOS VLSI 4th edition by Neil H. E. Weste & David M. Harris can also prove that what you solved is wrong
Thank you very much for explaining this in a great detail.
When we say we want to have equal rise and fall delay do we mean equal in worst case or in every possible case?
Worst case, I think..
at the start, why you say that in the pmos net we've 2C? I understand that in the N net you need that 3C because of R/3 and you have 3 so you obtain R. But shouldn't you have to put 1C , because the worst scenario is R in the pmos net?
For the PMOS to have same strength as NMOS, its width must be twice. That's why 2. You may look all values as multiple of some width W. Say 3W would be the width for each NMOS and 2W for PMOS.
Why we have to take size 3 for nmos. Why not other number... please anyone answer...
Because He wants a total pulldown resistance of R. Three resistors in series, each with a vallue of R/3 gives: R/3+R/3+R/3=R. I hope that helps..
Great video
How is it that everyone is showing the same 3 input NAND example Elmore Delay? Has no one in the history of the internet and text book figured out how to do do the Elmore Delay for a 3 input NOR gate? Sad reflection of educators for the EE field.
3 input NOR gate is not practically used
nice