VLSI DESIGN FLOW

VLSI DESIGN FLOW

[@tyagi8730]

Being from vlsi field I must aya It's a very good explanation

[@govardhannuneti3471]

Vhdl, v stands for vhic

[@leabhishekshrivastav3787]

Nice Explanation

[@naurinrisat71]

Thanks a lot sir for clear explanation

[@SRKumar-u9o]

Good explanation

[@PraveenKumar-li2gb]

Nice explanation 🙏

[@bhargavi16k67]

Good explanation

[@tvprakadeesh7914]

Good sir

[@elijahmikaelson8027]

24:41

[@rudranarayansahoo3237]

great explanation

[@raviraju1450]

Thank you

[@arshakmohammad8978]

sir feature undaa denike

[@brundagowda414]

Thank you sir, Good explanation

[@shubhamkanrar25]

Thank you sir

[@sudhirkumar-om7gm]

sir iska hindi me lecture nhi hi kya

[@subhashinisamal9865]

Where is dft?

[@addalapurivijithkumar573]

Dft step is once netlist generated.

[@RiteshKumar-kx2zt]

Sir please send notes

[@RiteshKumar-kx2zt]

Kisi ne notes Banya hei to pdf bana kar bhejo