Finally done with your challenging analog series , interview series and this rc rl series. My review is you teach very well and actually analyse things nicely ; I now have great intuition for RC ckts ; best wishes for this channel and my TI interview :) Thankyou
@@charishmarongali4787 intern to mil gayi isse, legit best resource hai, inke rc ckt ke first lec se ques tha mere interview mai, to bhai soch kitna accha series hai pura
How did you infer that the areas cut by x and y in 36:09 are equal? Is that equal everytime?? And at 38:24 WL = 10^3-10^6/2 is not very low. Infact it's very high(considering the magnitude of the frequency) Can you please comment on this sir?
Sir, how did you obtain Vmax/ root(3) for -3db level for parallel RLC after applying log? This differs from series RLC's 1/root(2) multiplier?
Written by mistake
Finally done with your challenging analog series , interview series and this rc rl series.
My review is you teach very well and actually analyse things nicely ; I now have great intuition for RC ckts ; best wishes for this channel and my TI interview :)
Thankyou
Bro is this enough for analog placements
@@charishmarongali4787 intern to mil gayi isse, legit best resource hai, inke rc ckt ke first lec se ques tha mere interview mai, to bhai soch kitna accha series hai pura
When will cohort 11-100 will come?
Waiting for it please give update about it
How did you infer that the areas cut by x and y in 36:09 are equal? Is that equal everytime??
And at 38:24 WL = 10^3-10^6/2 is not very low. Infact it's very high(considering the magnitude of the frequency)
Can you please comment on this sir?
1) Graph will be symmetric about Wo.
2) You can't take magnitude there.
is RL or RLC circuit necessary for gate aspirants in ECE
Yes, it is
Sir when cohort 11-100 will come please update as soon as possible 🙏🙏☺️☺️