Explained How Chips Are Designed
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- Опубликовано: 21 июл 2024
- From chip schematic, through libraries, chip layout, packaging, simulation and more. Explained by Joren Vaes. Thank you Joren.
Links:
- Joren's Linked In: / joren-vaes-mmwave
- Apheniox company website: www.apheniox.com/
- FEDEVEL courses: courses.fedevel.com/
Chapters:
00:00 What is this video about
00:45 Difference between analogue and digital chip design
05:49 Schematic of a chip, libraries, PDK
09:16 Simulation of a chip
12:16 Software used to design a chip
15:35 Price: How much does it cost to manufacture a custom chip
17:12 How to learn chip design
19:03 Doing layout of a chip
22:37 Parasitic extraction
24:11 Design rules
28:29 Layers in chip design
29:47 NMOS / PMOS transistor
39:58 Package design for a chip
46:26 Nanometers technologies - what does it mean?
48:17 What is FinFET and why it exists?
53:58 How many people design a chip?
56:36 Joren's chip
1:02:52 Why to design ASIC
1:06:39 CMOS vs Bipolar
1:10:47 Making resistors in a chip
1:14:05 Making capacitors in a chip
1:14:49 Thickness of metal layers
1:18:04 Parameters of a transistor
1:22:07 THz chip example
1:27:29 Making perfect chips from imperfect components
1:32:56 ESD protection in chips
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Would you like to support me? It's simple:
- Sign up for online courses hosted on our platform: marketplace.fedevel.education/
- Sign up for my Hardware design and PCB Layout online courses: academy.fedevel.com/
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- Or sign up for my Udemy course: www.udemy.com/learn-to-design...
It is much appreciated. Thank you,
- Robert 
Наука
![Sean Rii, Karyon, Sharzkii - Taungule [My Love] (Official Music Video)](http://i.ytimg.com/vi/eJoMuypbSzQ/mqdefault.jpg)
My mind has just blowed off. As an electrical engineer who worked on electronics for 10 years, after watching this video, I felt like there are still a lot of things to discover in this field. I never feel like I'm boared with routines. This was such a wonderful informative interview. I really enjoyed watching. Thank you a lot. Your video should be taught as one or two lectures for fresh grads or undergrads who pursue a study path in electronics.
These type of long videos are awesomes.
You explain many things at once.
Thank you, keep forward.
Hi , I'm a bs electronic student . thanks a lot for these videos. I learned more stuff in one simple video than 4 years of Studying
Sometimes I think this world is unfair.. some people are starting wars or watching stupid useless videos using tech created by very bright minds. Something must be really wrong. I can't imagine how far humanity would have been if everyone would had focused on science.
Thanks for the video !
Wow! What a journey. That was super interesting and inspiring. There are open source tools like Electic VLSI, Magic and Klayout that work with the Skywater PDK.
I really enjoy this type of content. This is the only channel where I can find such a deep level of explanation. Thank you. In future videos, I would love to learn more about the guest's CV if possible.
Very very valuable video. It showed me lots of insights.
Thank you Robert and Vaes
Nice talk!! We also design mmWave chips at the Technical University of Košice.
This is amazing content! This answered a lot of questions I had, but didn't have the vocabulary to search for (e.g. "dummy").
I know you already have some content on ESD, but looking at Physical Analysis of ESD failures could be really interesting & useful. Scanning Electron Microscope images aren't uncommon, but there are some exotic techniques like Photon Emission Microscopy, and Optical Beam Induced Resistance CHange (OBIRCH) which are interesting in their capabilities and sometimes also give insight about how things work on a different level.
Absolutely superb. Thank you Robert and thank you Joren.
Awesome job ! Thank you Joren for your presentation. Thank you Robert for your work too. This is a very valuable work, I love this kind of video I learn a lot !
Absolutely fascinating! Thank you for making these types of videos.
Very informative and exacting as always.
This has always been a little bit mysterious field for me, now it's a bit more clearer.
just randomly saw that video in my recommended feed, and I went like - "gotta drop everything else and watch this RIGHT NOW" - lol
:)
Thank you Robert and thank you Joren! This was a really interesting talk :)
Wow Im loving this, so far from anything I could ever get involved with but its so interesting to get an understanding of what is involved by talking to people I would never have access too.
Thank you very much, that was really interesting! All these insights, both technical and financial - very nice!
A Great interview no Doubt! Congratulations and thanks for sharing.
Impressive video, THX Joren and Robert.
This was a fascinating deep dive itno a super interesting world, thanks for sharing.
How cool, can’t wait to learn more about this later
A very interesting video. Thank you, Robert!
Excellent video.
Thanks so much for sharing the information.
Thank you for this deep dive!
Awesome video.. thank you ... most waited video
I am from Eastern Europe in year 2001. I went to IT high school because I wanted to learn everything about computers, we didn't have youtube than, and just dial up. After a while I understood that basically nothing useful I would learn there, just waist of time, by chance I went to uni for some special class and there was some beowulf system which they used to design some basic IC and other stuff this was moment when I have decided to don't go that route but I got what I wanted . Nowadays you can see that in few videos online amazing!
Hi Robert, first a thank you very much for all the videos you have made particularly about PCB design & layout. They have taught me so much valuable information which I use on an everyday basis when I layout PCBs! And then, since I cannot see how to contact you (I may of course have missed this information), I will allow myself a slightly off topic comment here with two suggestions for additional PCB layout related topics. The first suggested topic is how GND connected vias lining a PCB microstrip changes the trace's impedance as a function of via spacing and distance to the trace? The second is how component pin distance from the GND plane increases the EMR from these pins/components? I.e. is there a significant difference between the EMR from e.g. an SOIC component and a component where the pins are placed below the component (e.g. a UQFN package)? Hope you may find these topics to be interesting - & again many thanks for making these videos! Cheers, Jesper
He is from KULeuven, my uni, glad to see some talent from there showing up on your channel. Perhaps you can find some interesting people from Imec as well
Just found your channel - exciting to learn from
You!
Loving this channel since explored 😊
Very interesting informations , thanks Robert for making this amazing content
very interesting video! Thanks a lot
Wow almost 2 hours and I have no idea what they are talking about. I wish I understood but I don't maybe like .0001% but crazy how smart these guys are.
Thanks Robert for this video
Hovorim si, že taký Trenčiansky akcent má pán autor a odhadol som správne ,že bývame neďaleko od seba :) Velmi poučné videá
:)
Nice info, thanks :) 👍
This was very interesting!
Amazing video
Something I always wanted to know, great talk! Joren looks like Steve Jobs in his early days. Now it is clear to me why there are so less bugs in chips because any fault can cost the company thousands/millions or even billion of dollars. You cannot provide an update once it it is made. Remember the Intel Sandy Bridge fault. Imagine this process of design without the tools, in the 80s or in the 70s.......wow, sounds impossible to do but they did it! Nintendo for example, made custom chips for the Game & Watch series. Crazy if you think about it but they sold billions of devices so at the end they had their profit. Very interesting, nice video! Thanks for sharing!
Mr. Feranec. Any comment or analysis on the current ASUS/Gigabyte mobo Ryzen 7000 over Voltage meltdown problem ? I got a $0.01 on formation of unexpected fields on the chip pulling in more voltage. Gawd I wish I've had more Physics coursework! We'd love to hear f/ you and your connections on this !
This Joren guy seems like he knows some stuff :)
i don't even know how to comment on this ;d. i knew that modern (2006+) chips can contain resistors inside (made of silicon, etched in die's structure), but this whole transformer killed me :D.
Also i would like to see Robert having interview with developer of one of software using to simulate desing before sending it to foundry :D.
seems like designing chips is like designing pcbs, but in such small scale that you have to account for all physical phenomenas happening inside.
is it possible to revisit this topic and update the bond wire on already made design? :D
this gives so much perspective on higher level problems, like why and how ICs misbehave when traces on PCB are too long, or how it's possible to have only PCH's malfunction inside of mobile CPU
Merci pour votre video.
Isn’t there now a free gbl pdk but only for +100nm?
GF 180nm mcu is out indeed, and so is 130nm from Skywater
You talked about decoupling capacitors a few days ago... My question is why doesn't the IC have that capacitor, or why external components are needed, why can't they integrate everything inside the IC? Thank you.
Size of the package and manufacturing
Digital ics have capacitor cells made out of mosfet capacitances.I dont know about analog decoupling
Because the size of capacitance you can easily put on an IC is in the picofarad range; if you want more it will take a lot of space and therefore cost more than the functional part itself.
There are a lot of integrated decoupling on-chip, but as pointed out, this is much lower than what you can get off-chip, hence why usually both on and off chip decoupling caps are used.
probably due to size constraints, also might tend to be more failure points in the ic, so better to have them out side
Thank you
this is the first time ive seen this and ive been unable to find out due to it behind corporate paywall
I was wondering where I recognised Joren from, then realised that it was from his EE StackExchange profile picture. Small world :)
There is typically a system or asic architect who "knows" the chip and all of it's functions and interconnects.
Regarding "gate all around" construction, Samsung's foundry shipped their first 3nm node MBCFET silicon mid last year. It's the same idea as GAAFET but instead of rod-shaped gates they use sheets. Annoyingly, the customers they rushed this out for are the cryptocurrency miners (insert huge eye roll here), who were scrambling for lower power consumption. So most of that brand new 3nm tech is probably in a landfill by now. Samsung themselves probably won't ship useful SoCs based on MBCFET until later this year.
@@aphenioxPDWtechnology Makes sense. It wasn't super widely publicised anyway because it isn't really going to be relevant until they start rolling out the next generation of mobile SoCs. I was only vaguely aware of it because I was searching for something GAA related recently and stumbled across the press release!
I'm still waiting for a time that you can design your own ASICs at home with free EDA tools and send it to manufacture it in a company like JLCPCB.
That time is here, at least if you're okay with using an older technology. Skywater has its 130nm technology open and GlobalFoundries recently released one of their 180nm libraries. Together with xschem and klayout or magic you can get a long way. Manufacturing through Efabless gives you a nice start.
Maybe you already heard about it, but otherwise check out Tiny Tapeout 3 by Matt Venn. It's a start :)
How can you go to university at young age and know that you want to do this for the rest of your life?
what personally fascinates me is how you can create so complex things from such basic things as a transistor. how small things come together as one big thing to accomplis big and complicates tasks, much like evolution did over the course millions and billions of years. its fascinating how we humans have accomplished such great success in terms of computing power.
It's probably starts way before university. S. Jobs craved some lab equipment from HP CEO by phone at the age about 10 y.o.
at first tnx a lot for the great video
but
if I want to risk 50K~ 100K for design & sale $ I prefer a casino!😅
being 801 liker :)
Thumbnail correction: "HOW ARE CHIPS DESIGNED?"
You're welcome 😉
I like me this, I working with these device, Regards from México.
How much do you think someone with a job like this makes a year?