Working with Elon Musk, Steve Jobs, and Jeff Dean | Chris Lattner and Lex Fridman
HTML-код
- Опубликовано: 14 окт 2024
- Lex Fridman Podcast full episode: • Chris Lattner: The Fut...
Please support this podcast by checking out our sponsors:
Blinkist: blinkist.com/lex and use code LEX to get a free week of premium
Neuro: www.getneuro.com and use code LEX to get 15% off
MasterClass: masterclass.co... to get 15% off annual sub
Cash App: cash.app/ and use code LexPodcast to get $10
PODCAST INFO:
Podcast website: lexfridman.com...
Apple Podcasts: apple.co/2lwqZIr
Spotify: spoti.fi/2nEwCF8
RSS: lexfridman.com...
Full episodes playlist: • Lex Fridman Podcast
Clips playlist: • Lex Fridman Podcast Clips
CONNECT:
Subscribe to this RUclips channel
Twitter: / lexfridman
LinkedIn: / lexfridman
Facebook: / lexfridmanpage
Instagram: / lexfridman
Medium: / lexfridman
Support on Patreon: / lexfridman
"If you ask a lot of dumb questions you get smarter really quick"
Only if you have access to the smart people in the first place.
@@favesongslist information
@@huh5134 ? if you ask dumb people you will most likely remain dumb!
I'm gonna note this down
Yes but only if that person who ask dumb questions is willing to learn
Chris Lattner is so inspiring! Thanks you Lex!
Hi Lex. Will love to see Jeff Dean in your next one!
Great video! Thanks for making it!
when are you interviewing Jeff Dean?
I'm certain that Lex has asked, but Jeff declined.
Designing chips is not a simple thing. I work writing verilog for FPGAs and it's not an intuitive thing, and that's chip designing on "easy mode". Designing an ASIC, not an FPGA is a whole other level beyond that.
I was learning the wiring of 32-bit adder transistors and it was already complex from a Graph theory point of view. How complicated does it get if you want to understand something like a GPU?
@@acadianalien super late reply but if you're still interested I can give you more or less of an answer (I'm not an expert, but I've taken a VLSI class and TA'd digital electronics in college)
It turns out most of digital design is automated. No one in their right mind would start by figuring out the individual wire paths for each FET because that would be pure insanity. You tend to start very abstract, and develop a high level view of how your circuit will work at a system level, using something like SystemC. You validate that design, through tests and formal methods, and then go down a layer in abstraction. You then specify the lower level design (possibly down to gate level, but not necessarily) using some HDL, like Verilog or VHDL. Note that you don't do the entire design at once, you separate them into modules with clear interfaces, which you can then connect to create your entire system, similarly to how people construct software applications. Once again, you validate if your modules and overall design are logically correct through tests and formal methods. Now, things start to get interesting. If you're using an FPGA, your description of the circuit will be synthesized into something that the FPGA hardware can "understand" to implement your design physically. Naturally, the synthesizer needs to know the target FPGA, similar to a compiler. At this point, it is also possible to know through static analysis if your design is not only logically correct, but if it also meets timing constraints (the shifting of gates take time, and you have to make sure that all the information has time to propagate in the relevant paths). If you're doing some sort of ASIC, then you need to use some library the contains gates/flip-flops/registers implementations that comply with the specifications of the foundry you will be sending your design to. Then, the gates in your design will not only have a name like AND, but will also represent some physical AND gate, with its timing, power and area characteristics. This is mostly done automatically for you. You can once again verify your design (logic, timing, area, power) at this phase through static analysis, although these are estimated, since you don't have the wire lengths or how they will interact physically. Then, you go into place-and-route, which means that each of those gates will be place in a position that will correspond to their final position in the silicon wafer. Once again, this is done for you. Now, that is basically the lowest level model you can get of what your design will actually look like, and simulations here should (note the should) be very close to the real deal. Circuits can go through many tweaks here so that they fit constraints, both through human and machine feedback loops.
Although this is still hugely complex - automation, abstraction and modularity are the reason why hairless apes like ourselves all this context inside our brains at once.
Pretty insane and beautiful that this is what allows us to communicate like this.
Anyway, if anyone has any corrections, please throw them at me.
Perfect ending to a fantastic clip.
Amazing clip!
If you live each day as it was your last, someday you'll most certainly be right ~Steve jobs
5:19 Arts Technica level....
Brilliant...
Dude looks like a young Bill Belichek.
Nice person.
Bill would be dope get him on the show but it would have to be after Christmas
Chris went to the University of Illinois , H.A.L was conceived there🤖
Apple Will buy A Chip Company that improve Camera Chip for iPhone 14 with Better Photos and Videos in killer idea.
Tesla Will buy an AI that Improve Battery and Opporate for FSD in Tesla also Apple for AI Chip like for Camera snd FaceID.
From this clip Lattner strikes me as a people-pleaser. He strikes me as someone who has gained a lot of experience saying things people want to hear, because he is driven to say those sorts of things. I find it difficult to imagine him saying something which he knows will be wildly unpopular. But I guess in this world, it takes all types…
I think in his field being right and working with others is extremely important. So I can’t imagine him getting so far by just being a people pleaser. Extremely difficult to answer hard questions by doing that.