How to Reduce Power Regulator Switching Noise | Schematic Capture
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- Опубликовано: 9 июн 2024
- How does power regulator noise couple around a PCB layout? When thinking about parasitics, this is a crucial concept to understand in order to avoid glitching and high-speed signal failure. Technical Consultant Zach Peterson explores this, displacement current, current loops, and more.
0:00 Intro
0:48 Power Regulator Switching Noise Overview
3:02 Current Loops
5:52 Switching Nodes and Loops
6:49 Displacement Current Reduction
10:17 Typical Parasitic Capacitance Reduction
12:18 Changing the Layout
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Great video! I haven't thought about placing the power return path on the bottom layer yet. I'm worried about the impedance high frequency current might see because auf the vias, that are essentially inductors in the higher frequency range. I'd like to point out the fact, that high frequency return currents flow as close to their exciting trace as possible. The large loop you have drawn will be actually at the inner surfaces of the top side traces facing each other. So, making the gap between SW copper and ground copper on the top layer as small as possible, will reduce the parasitic inductance effectively. But placing the return path to an other layer and shifting the electric field orientation with that's, could be attractive in some situations. You've also mentioned the problem with capacitive coupling between SW nodes and signal traces on the top side. I like to surround the switching circuit with a ground fence that has closely vias to a solid ground plane. The electric field will be drawn to that fence and do less harm to signals behind it. Best wishes, Max
good video!
Glad you enjoyed it
Can you please explain me,
I have 7809Ic and my Vin is 12V , if I need to route both Power line what should be the clearance between 9V and 12V traces and how do I route ground for return path for same traces?
Or do I route 12V ,GND,9V traces to keep in mind return path?
Does the di/dt loop design you explained have greater impact on radiated emission than dv/dt loop? The rise/falltime are much more steep on the dv/dt loop, hence higher frequencies. Also is it better from a radiated emission point of view to route the return path on same layer rather than letting the return path go where it is lowest - under the inductor?
It's not really fair to say that the di/dt rate is different from the dv/dt rate or that one of these has more impact on radiated emissions. The gate driver used in a switching regulator will output a pulse that has some voltage and current, the pulse is a response on a conductor or transmission line due to switching of a driver. The di/dt generates a changing magnetic field, which then causes radiation. Similarly, the dv/dt generates a changing electric field, which also causes radiation. The two fields are related by Maxwell's equations, and when you have the two fields changing they will create an electromagnetic wave: you cannot have one field without the other.
If you're talking about measuring radiated emissions from a current loop, you will be measuring a voltage induced in a conductor loop due to changing magnetic flux (this is just Faraday's Law). In general the emissions you produce will have greater magnetic flux when the size of the loop is larger. This is why we always say to have a tight return path in a PCB, this means to ensure the current path through ground is closer to the signal conductor in order to make the loop area (and thus the changing magnetic flux) as small as possible.
It seems like such a delicate dance to manage Cp and Lp. Is there any board simulation software that can help you be smarter with the board layout. For instance, I use Fusion 360 cad/cam software and I’m able to do structural stress analysts of the part and optimize the design based on the results.
What you're talking about is something that would map Cp and Lp between one point and any other point on the board, that is a complex 3D problem requiring a solution to Poisson's equation in an arbitrary system. Computationally complex I mean.... I don't know if there are field solver applications that automate that specific analysis, I'm sure you could program that into COMSOL though.
Great video! If an application/design is having that many issues with parasitics and needing filters/components to rid the issue, wouldn’t removing the voltage regulator, and replacing it with Zener(s) rated at desired voltage(s) be a better overall design decision (in the end) as it also saves space and is much simpler to work with? A voltage regulator (by design) is supposed to ‘simplify’ the design, but ultimately instantiates a myriad of new issues. Thank you Zack, could you please help me/us to understand what benefit the regulator has over a common Zener(s)? Kindest Regards
It depends on the performance characteristics you need to hit in your system. If you're not worried about power conversion efficiency and you can withstand any losses across that series resistor in front of the Zener then go for it. Not all systems can accept that level of efficiency. Also once you get to higher powers, which is not necessarily outside the realm of some common digital systems, you'll start burning up components. There is another issue in the way switching regulators can eliminate noise, they can essentially trade low-frequency ripple for high-frequency switching noise. If you really wanted to swap out that regulator because noise was a problem, then a better option would be an LDO as these can provide high current and will not get crazy hot as long as the headroom is low.
When you suggest increasing (or reducing) the distances between things to change the magnitude of coupling, the inverse square law always applies, right? I always anticipate mention of the inverse square law when watching PCB videos, but I hardly ever hear it.
This is a good question but the answer is "no". The reason is that the inverse square law only applies for a point source, or when you are far enough away from the source (far field) such that the source looks a lot like a point source. On the PCB, you are either dealing with a cylindrical radial dependence (think the space around a trace, so 1/r dependence), or you are near a plane (constant E field). There is a transition region which is treated well in the quasi-static approximation used in 2D MoM or BEM solvers that are used to calculate the electromagnetic field around a transmission line where, eventually, the field amplitude scales to a 1/r^2 dependence, but only in the far field as I mentioned above.
Hi, great video thanks. I am currently desining a BMS and wanna supply with external power source for safety reasons. I dont know the power source noise freq but I wanna do my best to reduce as much noise as possible. Therefore I wanna add a dc input power filter circuit in my pcb. I am trying to learn how to do that because the IC I am using doesn't give me any directions or circuits for external power source. Can you give me some suggestions. I figured I can use CM chokes and Y caps. Or Ferrite beads but dont know how to choose the values. I have 48v dc power source to supply my IC.
What specific noise are you trying to reduce? Do you want to reduce output switching noise, input noise on the line voltage, or something else? The filter you need to use depends on the type of noise you want to reduce, so if you can identify that first then you can determine what type of filter you should use.
When you say move traces away from the regulator, how do you know how far is far enough? 5 Mils, 100 mils, or what is a good rule of thumb?
HI Skyler, great question! I have not ever seen a good rule of thumb. This topic of noise coupling from a switching regulator to nearby data lines has been the subject of a certain DesignCon paper, and it was found that the amount of noise depends on multiple factors so it's difficult to generalize to every situation. The recommendation of making traces short and direct helps reduce the coupling length between any of the conductors in the regulator and a nearby trace. The other rule regards how the board is laid out, if laid out properly you can prevent routing signal lines close to the regulator circuit anyways, so you can prevent the problem.
If you must route close to the regulator, then you might want to consider a much more conservative rule than the 3W rule between traces. This is because with a fast regulator, you can get big signal swings compared to the case of two parallel traces producing crosstalk. So for example, a small switching regulator could have an edge rate in the current loop somewhere on the order of 20 A/microsecond or higher. That's at least 10x what you might expect from a typical digital signal, so you might consider something like a 30W rule. Obviously those rules do not totally eliminate noise, you'll still want to test or simulate this!
Some vias on capacitor 0V so the return current can return back under the inductor on the 0V layer instead? Makes the loop minimized as much as possible!
Yes you can use vias. I showed single layer just so that people can see how to trace out the return current loop and it is clear where the current is flowing. But in another project video I did it using vias to the back layer as you describe.
Hi zack, what about reducing the input noise created by the switching regulator?
When you say "input noise", which noise do you mean? Are you referring to the dV/dt and dI/dt action of the switching elements in the regulator circuit?
One of the trends in switching regulator design is pushing the PWM frequency higher, which then requires faster edge rate. The result is that you can get lower ripple on the output and use a physically smaller inductor, or you can more easily design a multiphase converter. The drawback is the faster edge rates produce more radiated noise. So the trend is towards more noise being produced by the regulator, not less!
@@Zachariah-Peterson thanks for your reply, I'm more specifically referring to the noise induced back on on the input line. For example, im working on a buck converter that I'm powering from a 12V supply, and i can see on that 12V input line some spikes that are in sync with the switching action of the converter. How would one go about filtering or eliminating this induced noise from the input line? Thanks!
@@YoussefEl. Look up "buck converter snubber", I think.
Attention also needed at Vin. To reduce the noise, minimize the loops on both side:
large Cap ---- small cap ---- mosfets ---- inductor ---- small cap ----- large cap.
There are also other techs help reducing the RE, like spread spectrum, integrated cap, shielded inductor.....
Bringing the ground plane close to sw node may cause a lot of problems that may be hard to identify. Large sw node with a close proximity of GP creates a capacitance driven by high dv/dt. This reduces efficiency and may cause instabilities caused by current flowing through this capacitance. It may create an emi source as the current for this capacitance have to be delivered by the power net. The best solution is to make the sw node as small as possible.
Yes I understand what you're saying and I pointed that out in the dV/dt term. But this can help reduce switching noise coupling into other circuits through both capacitance and inductance as you reduce the mutual capacitance to some other circuit and reduce the inductive loop area. Also sometimes you don't have a choice as the SW node is on a dense high layer count board with controlled impedance lines elsewhere in the layout, so you're forced to put it closer to the plane. I agree with you though if you make the switching node physically small within some limits then you can compensate for a closer ground region. I guess it's all a balance you have to find.
@@Zachariah-Peterson thank you for reply and as you said - it is all about the balance, possibilities and compromises you have in your layout.
Thank you for your work!
Why not pour GND under the SW node?
You can do that, and bringing the GND closer to the SW node will reduce the mutual (parasitic) capacitance and inductance. We talked a bit about how that affects capacitive and inductive coupling to other circuits in another video:
ruclips.net/video/4DSsete22Zw/видео.html
Some application notes will recommend doing this as well to provide a tight, predictable return path. We have another video on two-layer power regulators boards coming out this week, where the current loop completes on the back layer instead of the same layer.
The tradeoff is that the SW node's self capacitance couples more strongly to the nearby GND and creates a current loop that bypasses the shunt recitfying element (in this case, a MOSFET or diode). This is only really important when you have very fast switching PWM signals as they will have high enough bandwidth to bleed some power past the other parallel elements in the power regulator circuit.
How is the concept of "reduce the parasitic inductance for less noise" reconciled with the fact that we have a relativity huge inductor deliberately placed in that loop?
We want to eliminate mutual inductance between that loop and any other circuit that might receive that noise. So yes, the loop has inductance due to the actual inductor, but it is the mutual inductance between the switch node copper and all other copper we would want to minimize. Hopefully that makes sense.
Can you add some sound proofing to the room so it doesn't sound like you're in a bathroom? No hate. It'll just make your videos be a little more professional. Cheers.
We're at the mercy of our rented office space, but I'm looking for a new office with more space and better acoustics