I've been doing a lot of CAN bus firmware coding lately which is the only differential pair signalling I work with, and while I kinda knew what was going on with the physical layer, this just spelled it out for me perfectly. As a coder and not a PCB designer, it's always helpful to have a deeper understanding of how our hardware works. Thanks.
Your vids have been very instrumental in our project development. I'm currently working on daughterboard where it gets 24 VAC power from the mainboard. Both designs utilized half-wave rectification hence one line is referenced as ground. Since the power connectors are just clip and screw terminals, we can easily switch lines 1 and 2. This shouldn't be a problem cause there are no other wirings utilizing common ground which will cause a short if not both line 2 are connected to the 0V terminal. The mainboard and daughterboard communicate via CAN protocol (or TWIA) and works smoothly when the power wiring is correct. If one wiring is reversed, the MCU gets to around 30 Celsius when in normal conditions it is only around 16 Celsius. The receiver also misses a couple of messages. I checked the datasheet and found out that the CAN lines are pulled up and down to its rails. CAN ICs with isolation features is certainly not an option for us at this stage.
Hi sir I'm routing engineer in India but i know some basic of difference pair concept after seeing this video I clearly understand what's the matter in side the differencial pair routing thanks for this good work sir .I have 1.5 years experience in ATE boards routing. if you need any vacancy in your company please let me know sir. I have know pair routing,pair matching, length matching, force and senese routing and know some tools like allegro and pads tools. Thank you for this video sir
Regarding different ground references, take care that your IC can withstand the voltage value respect to its own gnd, or it could be damaged. I like your videos style. Blankboard, ilustrations and focus on information.
Thanks for the compliment! That is a good point about the level of GND offset, although I remember reading from Lee Ritchey, one of the pioneers in designing with SerDes, that differential pairs can withstand very high GND offsets.
Remember each half, the _p and _n, of this type of differential pair references to GND and not each other. They are really 'just' complementary single-ended signals. So the return path is GND and not the other _n or _p. Else the trace length matching would introduce gross impedance humps, generating reflections and EMI. ONLY transformer coupled differential pairs are truly balanced and differentially refering to each other and not the GND.
@@ihtsarl9115 Yeah I am not good at explaining. Take the time to watch this: ruclips.net/video/qEI31nNltFY/видео.html My point is just that some designers believe you dont need GND returns with a differential pair. It depends as usual, but only true differential that is isolated from the reference plane has the energy between the two differential pair. Mostly we have pseudo balanced and the energy is between each diff line and GND. So routing we need to have uninterupted GND return all the way unless it is 'true' balanced using transformers on both ends.
Great video as usual, before explaining length matching styles, it would be great to show how to determine length matching requirements. From what I understand, app notes are a terrible source for this information and the actual requirements can be very lenient.
Yes I agree, application notes should be tested until proven correct. One thing I've noticed is that some of the objectively bad design practices (at least for high speed/high frequency boards) originate from app notes that are very old, and they are probably regurgitating advice from even older app notes... it all gets taken out of context and no one even bothers to check the date on the documents. As far as length mismatch allowances go, they are normally specified in the spec for the signaling standard. Sometimes a component vendor that uses a high speed differential interface will describe the length mismatch in terms of a length, but that length will be different if you are using striplines instead of microstrips, different materials in the stackup, and so on... EDIT: for USB 2.0, I believe the maximum allowed skew is something like 100 ps, which is very generous.
1. Does the differential lines needs ground plane under them? (It's not need in my opinion) 2. How we can determine the width of the track and space between tracks? I asked this question to my fabricator but they didnt answer it clearly. 3. Is it possible to design impedance controlled pcb with 2 layer stackup only. (both layer has got signal and ground plane) 4. Is there a feature in altium to check signal integrity issue (crosstalk, ringing etc). Thanks in advance.
Hi Zafer, I'm so sorry I just noticed this, I originally posted a reply to this but RUclips deleted it because it contained a link! Here are the answers to your questions: 1. No, technically it's not needed. It is needed to define the characteristic impedance of an individual single-ended trace. 2. Your fabricator will use an application like Polar or Saturn to determine this, probably using a boundary element method simulation. You can technically do it by hand if you can calculate the mutual capacitance and the mutual inductance between two rectangular traces. I've never seen a good derivation of these two quantities directly for paired conductors over a ground plane. There are several ways to do it (Green's function, reciprocity principle for TEM-supporting structures, direct definition of mutual impedance...), here is a guide on this topic from NIST: nvlpubs[dot]nist[dot]gov/nistpubs/Legacy/circ/nbscircular544.pdf 3. Yes of course, I'm just not sure you would hit a typical impedance target on a standard 2-layer stackup unless the traces and spacing are very large, so it's not really practical. Consider a typical SIG/GND/PWR/SIG stackup with 8 mil dielectric between top layer and GND: you would have somewhere in the neighborhood of 14 mil trace width with large separation needed to hit 50 Ohms/100 Ohms impedance. If you were on 2 layers with standard stackup and dielectric thickness of 60 mils, your impedance values nearly double... Like I said, it would take huge traces and big spacing on a 2-layer board. 4. Yes there are these features, see here: techdocs[dot]altium[dot]com/display/ASIAE/Performing+Signal+Integrity+Analyses - This guide is older, it's for Altium v15 I think, but the same features and workflow are used in the newest version.
@AltiumAcademy When potential difference between 2 GND’s is not same as it’s -0.5 then why its not affecting the voltage of differential pair ¿ if I see the equation then it’s gnd1 and gnd2 which are not same potential so it should add to the voltage of diff pair mathematically
The ground offset does affect the voltage of the differential pair equally, which means the DC adds a common mode component to the signal's voltage level. Differential receivers measure the voltage difference between the two traces, so because the two traces are each offset by the same common mode DC component the differential receiver is eliminating the common mode DC offset. This is one of the main reasons that differential pairs were originally used in high data rate serial connections over cables; they can withstand the voltage offset that can arise between two pieces of equipment (each with floating grounds).
Writing -1 should not be literally construed to mean -1V. The signal can have DC offset that is common to both signals and they can both have a positive voltage, but the differential voltage measured at the receiver will still be negative or positive value with equal magnitude.
Hi, I wonder where the return current flows in diff pairs for an example USB2.0. And why ground plane reference for an USB2.0 is a must. Probably you have made video about that :)
Hi Ilia, thanks for watching and these are great questions. I can tell you that the return current for a differential pair is technically the other trace, although in reality there is some return current capacitively coupled into the nearby reference plane. This is why the return nearby ground affects the impedance, it creates some additional capacitance that appears in parallel with the self-capacitance between the two traces. The reason we need ground in USB 2 is to set the impedance of the traces to the required value, and placing the GND closer to the traces allows the traces to be made thinner when they are being designed to a target impedance. USB 2 signals can be routed as individual traces, meaning they can be separated. You have to be careful with this because some noise might appear on one trace, so it would not be common-mode and wouldn't be suppressed. Also the individual trace impedances have to be set to the required single-ended value to ensure correct termination at the driver/receiver. Another good reason to use GND in general is to provide a low-inductance return current so that you can reduce ground bounce. GND planes also provide some shielding and noise reduction generally, and this increases when the GND plane or pour is brought closer to traces.
@@Zachariah-Peterson for differential pair high speed signal transition we are using signal vias along with ground vias. My questions is if we are not used the ground via along with signal vias. What is the impact on the board and what are the consequences we have to face. Please correct me if my question is wrong.
Absolutely. Events doesnt occur instantly. Signals travel in the transmission line and it takes time. If there is a signaficiant lenght difference, this means that signals arrives to the receiver at different times. Signals in the shorter line reaches before the longer lines. So there is a time delay between rising (falling) edges of the receiver dif inputs. This means that the receiver interpretes wrong logic.
You don't have to think about length, but time. Signals must reach the receiver at the same time. And you obtain this by topically equalising the length of the traces
Sometimes, the signals just transmit with differential pairs and no gnd wire. then what is the reference point? Does differential pair refer to each other?
Diff pairs aren't perfectly symetrical both in the physical construction and the actual signals propagating through them. The reference plane is the return path for common mode current, so it reduces the chances of that noise coupling elsewhere as well as providing a level of shielding from other aggressors.
The GND reference is always somewhere, even if it is just physical earth. In the case where there is no GND plane, the signals reference each other, but there is major benefit to having GND. The big reason is to prevent differential crosstalk between pairs and to ensure crosstalk from a single-ended trace appears as close as possible to a true common-mode signal on the victim differential line, that way the differential receiver will be able to cancel the common-mode signal.
Hello, my apologies as this reply should have been posted awhile ago, so I'll post it here now. Technically yes you can, you can route SPI to a differential interface converter. Probably the easiest to use will be CAN bus. Just look for an interface converter or CAN transceiver on Google or on Octopart. Just note that those interfaces are single-ended by definition. You should ask yourself, why exactly would you want to use differential pairs in that situation? Just note that SPI, I2C, and the like are not really meant for situations where you might need to make long routes between systems that might have some ground offset. Better to use something designed for long-range. If you're just routing between two boards with a small ribbon connector, and their power is on the same circuit, why not just supply power from one board to the other, and then carry a GND line along your cable to ensure low loop inductance? Just about every MCU board you can find will do this, they don't separate out power onto different circuits and then use differential lines for data. You don't get much additional benefit from differential pairs in that situation. Just something to think about as you shouldn't have to overdesign your board.
Yes, this is true, but fundamentally is not relevant for the purpose of this video. Usually every engineer must know that the CM is not something really good and need to be kept at lowest possible level.
I've been doing a lot of CAN bus firmware coding lately which is the only differential pair signalling I work with, and while I kinda knew what was going on with the physical layer, this just spelled it out for me perfectly. As a coder and not a PCB designer, it's always helpful to have a deeper understanding of how our hardware works. Thanks.
Your recent videos have been really helpful. Are you considering making a video about impedance matching networks, especially for antennas?
Request from my side also!!
We have lots of requests for videos but I will add it to the list. Thanks for watching!
Yes I’m interested as well
Your vids have been very instrumental in our project development. I'm currently working on daughterboard where it gets 24 VAC power from the mainboard. Both designs utilized half-wave rectification hence one line is referenced as ground. Since the power connectors are just clip and screw terminals, we can easily switch lines 1 and 2. This shouldn't be a problem cause there are no other wirings utilizing common ground which will cause a short if not both line 2 are connected to the 0V terminal. The mainboard and daughterboard communicate via CAN protocol (or TWIA) and works smoothly when the power wiring is correct. If one wiring is reversed, the MCU gets to around 30 Celsius when in normal conditions it is only around 16 Celsius. The receiver also misses a couple of messages. I checked the datasheet and found out that the CAN lines are pulled up and down to its rails. CAN ICs with isolation features is certainly not an option for us at this stage.
Clear & easy to understand
Thanks
Glad it was helpful!
Your introductions are very good and clear for understanding. Thank you so much!
Glad you like them!
Hi sir I'm routing engineer in India but i know some basic of difference pair concept after seeing this video I clearly understand what's the matter in side the differencial pair routing thanks for this good work sir
.I have 1.5 years experience in ATE boards routing. if you need any vacancy in your company please let me know sir. I have know pair routing,pair matching, length matching, force and senese routing and know some tools like allegro and pads tools. Thank you for this video sir
Regarding different ground references, take care that your IC can withstand the voltage value respect to its own gnd, or it could be damaged.
I like your videos style. Blankboard, ilustrations and focus on information.
Thanks for the compliment! That is a good point about the level of GND offset, although I remember reading from Lee Ritchey, one of the pioneers in designing with SerDes, that differential pairs can withstand very high GND offsets.
@@Zachariah-Peterson I agree, but when testing stuff that is supplied with more than 1000vdc things start to be frightening 😂
This is a great explanation of differential pairs! Thank you!
Glad it was helpful!
Remember each half, the _p and _n, of this type of differential pair references to GND and not each other. They are really 'just' complementary single-ended signals. So the return path is GND and not the other _n or _p. Else the trace length matching would introduce gross impedance humps, generating reflections and EMI. ONLY transformer coupled differential pairs are truly balanced and differentially refering to each other and not the GND.
that's confusing
@@ihtsarl9115 Yeah I am not good at explaining. Take the time to watch this: ruclips.net/video/qEI31nNltFY/видео.html
My point is just that some designers believe you dont need GND returns with a differential pair. It depends as usual, but only true differential that is isolated from the reference plane has the energy between the two differential pair. Mostly we have pseudo balanced and the energy is between each diff line and GND. So routing we need to have uninterupted GND return all the way unless it is 'true' balanced using transformers on both ends.
Thx for turkish translate
Excellent explanation! Thank you!
You're very welcome!
legendary pedagogy
Thanks a lot ❤
Excellent explanation
Glad it was helpful!
Great video as usual, before explaining length matching styles, it would be great to show how to determine length matching requirements. From what I understand, app notes are a terrible source for this information and the actual requirements can be very lenient.
Yes I agree, application notes should be tested until proven correct. One thing I've noticed is that some of the objectively bad design practices (at least for high speed/high frequency boards) originate from app notes that are very old, and they are probably regurgitating advice from even older app notes... it all gets taken out of context and no one even bothers to check the date on the documents.
As far as length mismatch allowances go, they are normally specified in the spec for the signaling standard. Sometimes a component vendor that uses a high speed differential interface will describe the length mismatch in terms of a length, but that length will be different if you are using striplines instead of microstrips, different materials in the stackup, and so on... EDIT: for USB 2.0, I believe the maximum allowed skew is something like 100 ps, which is very generous.
MIPI/CSI2 is very easy to do. Mentor Graphics will signal match distance to 0.1mm but the spec means you can track it like CAN bus!
@PCBFE we just did a couple videos on this and I think 1 of them went up last week, take a look in the channel and see if you can find it.
Can you please also explain how to design differential pairs on a single PCB and examples of where we could need them on a single PCB?
1. Does the differential lines needs ground plane under them? (It's not need in my opinion)
2. How we can determine the width of the track and space between tracks? I asked this question to my fabricator but they didnt answer it clearly.
3. Is it possible to design impedance controlled pcb with 2 layer stackup only. (both layer has got signal and ground plane)
4. Is there a feature in altium to check signal integrity issue (crosstalk, ringing etc).
Thanks in advance.
Hi Zafer, I'm so sorry I just noticed this, I originally posted a reply to this but RUclips deleted it because it contained a link! Here are the answers to your questions:
1. No, technically it's not needed. It is needed to define the characteristic impedance of an individual single-ended trace.
2. Your fabricator will use an application like Polar or Saturn to determine this, probably using a boundary element method simulation. You can technically do it by hand if you can calculate the mutual capacitance and the mutual inductance between two rectangular traces. I've never seen a good derivation of these two quantities directly for paired conductors over a ground plane. There are several ways to do it (Green's function, reciprocity principle for TEM-supporting structures, direct definition of mutual impedance...), here is a guide on this topic from NIST: nvlpubs[dot]nist[dot]gov/nistpubs/Legacy/circ/nbscircular544.pdf
3. Yes of course, I'm just not sure you would hit a typical impedance target on a standard 2-layer stackup unless the traces and spacing are very large, so it's not really practical. Consider a typical SIG/GND/PWR/SIG stackup with 8 mil dielectric between top layer and GND: you would have somewhere in the neighborhood of 14 mil trace width with large separation needed to hit 50 Ohms/100 Ohms impedance. If you were on 2 layers with standard stackup and dielectric thickness of 60 mils, your impedance values nearly double... Like I said, it would take huge traces and big spacing on a 2-layer board.
4. Yes there are these features, see here: techdocs[dot]altium[dot]com/display/ASIAE/Performing+Signal+Integrity+Analyses - This guide is older, it's for Altium v15 I think, but the same features and workflow are used in the newest version.
nice for beginners, i will address that video to my students.
BTW< please do video about antipads for single end and differential signals.
Great suggestion!
great video.thank you.waiting for more education video.
More to come!
Nice explanation 🙏🙏
Thanks and welcome
@AltiumAcademy When potential difference between 2 GND’s is not same as it’s -0.5 then why its not affecting the voltage of differential pair ¿ if I see the equation then it’s gnd1 and gnd2 which are not same potential so it should add to the voltage of diff pair mathematically
The ground offset does affect the voltage of the differential pair equally, which means the DC adds a common mode component to the signal's voltage level. Differential receivers measure the voltage difference between the two traces, so because the two traces are each offset by the same common mode DC component the differential receiver is eliminating the common mode DC offset. This is one of the main reasons that differential pairs were originally used in high data rate serial connections over cables; they can withstand the voltage offset that can arise between two pieces of equipment (each with floating grounds).
can't thank you enough . keep it up
You're welcome!
when measuring signal-, it probably is not -1 if considering common mode signal.
Writing -1 should not be literally construed to mean -1V. The signal can have DC offset that is common to both signals and they can both have a positive voltage, but the differential voltage measured at the receiver will still be negative or positive value with equal magnitude.
Hi, I wonder where the return current flows in diff pairs for an example USB2.0.
And why ground plane reference for an USB2.0 is a must.
Probably you have made video about that :)
Hi Ilia, thanks for watching and these are great questions. I can tell you that the return current for a differential pair is technically the other trace, although in reality there is some return current capacitively coupled into the nearby reference plane. This is why the return nearby ground affects the impedance, it creates some additional capacitance that appears in parallel with the self-capacitance between the two traces. The reason we need ground in USB 2 is to set the impedance of the traces to the required value, and placing the GND closer to the traces allows the traces to be made thinner when they are being designed to a target impedance. USB 2 signals can be routed as individual traces, meaning they can be separated. You have to be careful with this because some noise might appear on one trace, so it would not be common-mode and wouldn't be suppressed. Also the individual trace impedances have to be set to the required single-ended value to ensure correct termination at the driver/receiver. Another good reason to use GND in general is to provide a low-inductance return current so that you can reduce ground bounce. GND planes also provide some shielding and noise reduction generally, and this increases when the GND plane or pour is brought closer to traces.
@@Zachariah-Peterson Thank you for the answer
Why ground via is required in differential vias. What is the main reason. What will happen if we were not used the ground via.
I'm not sure what you're referring to, could you please clarify what you mean by "ground via"?
@@Zachariah-Peterson for differential pair high speed signal transition we are using signal vias along with ground vias. My questions is if we are not used the ground via along with signal vias. What is the impact on the board and what are the consequences we have to face. Please correct me if my question is wrong.
The question is, if I use impedance profile for my differential pairs, should I also focus to the matching lengths of the differential pairs?
Absolutely. Events doesnt occur instantly. Signals travel in the transmission line and it takes time. If there is a signaficiant lenght difference, this means that signals arrives to the receiver at different times. Signals in the shorter line reaches before the longer lines. So there is a time delay between rising (falling) edges of the receiver dif inputs. This means that the receiver interpretes wrong logic.
You don't have to think about length, but time. Signals must reach the receiver at the same time. And you obtain this by topically equalising the length of the traces
Sometimes, the signals just transmit with differential pairs and no gnd wire. then what is the reference point? Does differential pair refer to each other?
Diff pairs aren't perfectly symetrical both in the physical construction and the actual signals propagating through them. The reference plane is the return path for common mode current, so it reduces the chances of that noise coupling elsewhere as well as providing a level of shielding from other aggressors.
The GND reference is always somewhere, even if it is just physical earth. In the case where there is no GND plane, the signals reference each other, but there is major benefit to having GND. The big reason is to prevent differential crosstalk between pairs and to ensure crosstalk from a single-ended trace appears as close as possible to a true common-mode signal on the victim differential line, that way the differential receiver will be able to cancel the common-mode signal.
Can I use differential pair for UART, I2C and SPI clock and data lines?
Hello, my apologies as this reply should have been posted awhile ago, so I'll post it here now.
Technically yes you can, you can route SPI to a differential interface converter. Probably the easiest to use will be CAN bus. Just look for an interface converter or CAN transceiver on Google or on Octopart. Just note that those interfaces are single-ended by definition.
You should ask yourself, why exactly would you want to use differential pairs in that situation? Just note that SPI, I2C, and the like are not really meant for situations where you might need to make long routes between systems that might have some ground offset. Better to use something designed for long-range. If you're just routing between two boards with a small ribbon connector, and their power is on the same circuit, why not just supply power from one board to the other, and then carry a GND line along your cable to ensure low loop inductance? Just about every MCU board you can find will do this, they don't separate out power onto different circuits and then use differential lines for data. You don't get much additional benefit from differential pairs in that situation. Just something to think about as you shouldn't have to overdesign your board.
Keep in mind there's a limit on how high the common mode voltage difference can be. Too high and you'll get problems..
Yes, this is true, but fundamentally is not relevant for the purpose of this video. Usually every engineer must know that the CM is not something really good and need to be kept at lowest possible level.
It says in the video that you are technical consultant. That is enough.