Automated Code Checks to Accelerate Top-Level Design Verification

Presented at DVCon Europe 2021
Session T3.3
Integrated circuit designers are under constant pressure to deliver bug free code that meets evermore rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design process.
The two major methods that designers can leverage to detect bugs are static linting and simulation. Linting requires low set up and can detect a class of bugs based on the syntax of the code, although does tend to report many potential issues that have to be analyzed and is limited when examining the sequential operation of a block. Simulation is focused on the code operation but requires a greater degree of set up, in the form of directed stimulus creation, which are usually not available at this stage in the process and will only detect issues in scenarios that the provided stimulus is examining.
What designers require for early and automated detection of implementation issues are fast and easy ways to set up static checks for the sequential operation of the code in an exhaustive fashion, without relying on user provided stimulus. Automated formal code inspection helps to rapidly eliminate errors in a piece of RTL, prior to functional verification and synthesis, while providing a fully automated, and simple use-model.
Presenter:
Nicolae Tusinschi - Onespin
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