"Don't miss the forest for the tree". We believe we are all well versed on 2nd and 3rd order effects as well as non-idealities. Interviews, most of the time, are conducted assuming ideal devices. Finally, be sure to check out the paper in the description of the video. This circuit is widely used as a minimum current selector.
To be honest, I agree with "Bob" at some points: The question doesn't mention any of the device size and device ratio which need us to make a lot assumptions. The device size and the actual current of I1/I2 affect the gate voltage of all of the transistor. For example, if I2
Hi there, I really enjoyed this circuit, thanks! I think you got the main point, and I personally like calling the circuit a min(I1,I2) generator. However, for I1=I2, I think you should not say that "there is no minimum" (hear at 7:58s). Mathematically, the minimum between two equal values is the value itself. So, for I1=I2, min (I1,I2) = I1 = I2. In that specific case, the circuit produces I/2, a value which is not the minimum.
Hi! Thank you so much for contributing to the discussion, we're glad you're here! Mathematically, this is absolutely correct. However, from a circuit perspective there's no minimum much like the inverter analogy. However, we appreciate the feedback and will work our best to be more concise next time. Thank you!
This is a fresh take on current mirrors! Love it! Never knew a selection function could be built by simple current mirrors. Also love the analogy too. It's amazing how you can come up with analogies on the fly. In an interview, I'd probably think of the inverter analogy only after it's over. Looking forward to more vids!
I think the challenge of giving a mixed signal/analog interview is presenting devices in a configuration that the person being interviewed hasn't seen before so they can think out what happens, but still have it be simple enough so it is not a spaghetti mess. Solving a DC operating point of something and then asking something like "which device falls out of saturation first as the input increases" is totally fair and expected.
Working as Analog IC design engineer. Was present on the numerous interviews from both sides. Few comments: 1. Open ended questions without details. 100% something to expect during the interview. The additional questions that candidate asks will easily show his knowledge level. 2. I like the way of working out the interview problem that you showing in your videos. Doing analysis out loud, making assumptions and not just giving the answer or say “i don’tknow” - that certainly the right way to crack the interview. 3. I agree with “Bob” that you’re probably not really a specialist in analog ic design. You’re making a lot of silly mistakes and miswords. So I would not recommend to learn technical stuff from your videos, but rather learn the way of working and try to solve or read how to solve the problem on your own. 4. I bet no fresh graduate will go farther than “this is cascode current source circuit” and if sizing and currents are correct, cascode is working, else - not. Idea of minimum current selector is quite not trivial and without reading the papers about “feedback class ab output stages” papers or books or something simillar, i would not expect answers into the right direction. 5. I personally used such circuit in the real silicon, as a part of ab output stage. Works perfectly well, one of my favourite architectures now.
Hi Volodymry, Thank you so much for your detailed feedback. We're glad to have you contribute to the discussion. Let us address some of your comments below: 1. Thank you, this is exactly what the aim of the content is. 2. See point 1 :) 3. Some of the team members have a career in analog design IC with plenty of experience. That being said, it is not our goal to teach anything related to design. That's why we don't focus so much on 2nd order effects or nonidealities before the ideal operation has been established. We operate from an assumption that folks watching our videos already have the technical know-how to answer some of the questions themselves. 4. We agree with you here! However, the point of an interview is to have the interviewee solve practical problems that they don't have much exposure to. That way we can really evaluate the degree of experience and problem solving skills that he or she may have. 5. We have implemented this architecture in SoCs as well. Hence, the reason we provided the question :)
In every analog circuits there is always room to dabate in everything. Its not precise science if you do not take into consideration about everything. Analog design is art and science in the same time.
I understand where "Bob" is coming from. Not saying anyone is right or wrong, but depending on the biasing will totally change the way the circuit behaves...including different than the description in the discussion.
How you arrive at your answer, the thought process, the assumptions and how you communicated those to your team mates are more important than being right. The best answer is arrived at when the team is in sync with each other. IC Design is a team play. I thought the circuit presented was a current modulator i.e. I2 modulates I1. Varying I2 varies VDS1 and I1 will change slightly due to channel length modulation by VDS1. But i enjoyed listening to your thought process.
Thank you so much for the sharing. In fact, this circuit is a well-known min. current selecting circuit. One can find a improved version using feedback control. See chapter 2 "operational amplifter speed and accuracy imrovement" by Vadim Ivanov, which is the best book for amplifer design.
Thank you for the nice video! One query: When I2 > I1; Vgs of M4 is high. That's understandable. But, "If I2 is high, source of M3 will be high" (Time stamp : 3:40) --- How you jump to this conclusion?
I think he's trying to say if I2 is high then the gate of M3 will be high, and that voltage is Vds2 + Vgs3, which will easily be high enough to keep M2 in saturation.
@@theabr4839 Does he not know that M3 & M4 are NMOS transistors? Because he got it flipped the other way as well on (time stamp 4:18). If M3 and M4 were PMOS, then his statement 3:40 and 4:18 is correct.
4:18 "The low vgs(m4) means source of M3 is low" ? I am confused because to draw less current(I2) shouldn't the source of M3 increase? Vg - Vs ---> lower Vs ---> higher I2 sounds incorrect. I think the source of M3 increases, Vg - Vs ---> higher Vs ---> lower I2 which is < I1. Help me on this.
Great content, thank you! Loved the analysis without taking any higher order effects, it's simple and elegant. Of course, we need to be a bit flexible here to buy your answer, which is kind out of the box. Would never get to the min function selection without guidance. To be fair, this sounds like interviewer function to drive the answer to this direction. Expected answer would be the cascode current mirror with I2>I1 (assuming proper sizes), Then, the interviewer could ask: "what if I1>I2" and so on... Bob failed miserably in understanding the "ideal" scenario. However, I think you should buy him a beer anyway, he seemed stressed. Liked the inverter analogy to reinforce your point too.
This is a quite tricky problem and the complete answer is Iout= ( I1 .I2)/(I1+I2)( if we suppose that all the transistors are identical).Personally I will never test a candidate with a such problem.To be fair it is a trivial problem (for me ) but a real nightmare for most Analog designers to find the result that I have just provide.Also is quite odd what you say in the video you have just solved it either I1>>I2 or I2>>I1 and what you say when I1=I2=I we get Iout=I/2.Now the real questions are what is (are )the imperfection(s) and how to solve it (them)?
I agree Bob did lost perspective of it being an interview question and showed arrogance, but friend, your comments in the video are as arrogant as his. Please don't fall in the same game.
If you're assumption of ideal devices includes a zero knee voltage, then yes, this would be a min function. Transistor length be damned. Also, the ratio of the current mirrors, imo, is irrelevant. You can just set I1 and I2 to be I1' = A*I1 and I2' = B*I2 where A and B are the CM ratios and then let the CMs have a ratio of 1. Unless we change the problem in such a way that we now care about the currents going through the diode connected transistors.
Hi James, Thanks a lot for stopping by! We decided to delete the thread to avoid people reaching out to Bob. You can find a copy of it in the description of the video. What's your verdict? Beer for Bob or Beer for ByTor?
Bob was acting like a fool but he had a minor point about the case when I1=I2 (even though his analysis was a little off). Since you didn’t mention any hard specs his point could be valid. I’ve had my share of dealings with these old design guys, and they can be totally way off base sometimes, but then sometimes in reviews they can catch things you never thought of, so it’s a good idea to stay on their good side :)
I understand that you are trying to make an inverter analogy for this case, but to be honest, I don't think it's fair to assume everything being "ideal" because *they simply don't exist in this world*. In your inverter analogy, if the inverter isn't ideal, the output would give logic 0 for 50% of the time and logic 1 for the other half of the time, which is still functioning as inverters, except now you are inverting random noises. Actually you can use this distribution to figure out the skew of the inverter and so on, but that's a whole other topic. But the point was that, even in the case when your input is vdd/2, inverters still "inverts" a signal. Whereas in this example, if I1=I2, and you still wanted to maintain the min(), you can't just say it is okay to output I/2, because min(I1,I2) is not equal to half of each quantity either. You have to put an asterisk in the case when you assume I1=I2 to say that min() does not hold or something. For example, mathematically speaking, min(10,10) can never equal to 5. And that's entirely okay. A better argument imo would be to say that even if you assume I1=I2, when these transistors are on *real* chips, process variation will make sure they are almost never equal, and so the min() will still hold in those cases.
Hi, Thank you so much for your comment, we're glad you're here! We would like to address your comment about non-idealities. You're correct, nothing in this world is ideal. However,, during interviews, 2nd and 3rd order effects are not talked about much (unless it's a position for a role that requires a lot of experience). The reason for this is that if candidates cannot infer how a circuit will behave ideally, then it's likely they don't understand the 2nd order effects either. The same analogy can be done with an amplifier. If it's biased correctly, then it works as an amplifier. If there's a step and it stops slewing or are close to the max/min swing of the amplifier it will behave non-linearly. Just because of that, it doesn't make it any less of an amplifier. We do appreciate your feedback very much though and will use it to make our future content better.
The fact they said vdd/2 is telling. Even in digital, let alone in analog, they should know pmos and nmos are different and why the "middle" voltage isn't vdd/2. (Though you could modify W/L_n and W/L_p ratios). (But again, you'd think they'd have basic concept of process corners, etc especially to be lecturing experienced analog guy comments online.
The circuit is interesting once one reads how it's used in a class-AB amplifier. However, the way it's presented here is too simplistic and lacks key details such as sizing. Finally, I don't think it's a minimum current selector like the way you present it. If I2 > I1, for example, M3 sure wouldn't carry I2 as its source is on higher potential than that of M4, but there's no guarantee that M2 would be able to carry I1 either as its drain potential would be lower than that of M1 and Ids isn't constant after Vds > Vdsat.
Thank you so much for the feedback and contributing to the discussion. Details, like sizing, tend to become irrelevant in an interview discussion as we're not designing anything. Instead the interviewer is after problem solving and how one can use fundamental concepts to decipher what the circuit is doing. Remember we're not trying to teach anything new nor are here to educate people about core concepts. Instead we're bringing real life interview questions to you and assume you have all the tools to solve the problem.
Everyone can have Bob tendencies... I looked at the mirror circuit and initially concluded a current controlled current mirror. I was reasonably sure but enjoyed the answer and detail.
Thank you so much for your comment and contributing to the discussion! We're not looking for everyone to agree with our answers, after all they're open ended questions. What we wanted to showcase, as you rightfully point out, is that some engineers can get stuck and caught up on things.
Hi Yunus, Thank you so much for contributing to the discussion! Could you elaborate what you mean by "many assumptions". We love feedback and would really like to understand how we can provide a better service to the community. Also, let's not forget the main point of interviews that is knowledge of basics, abstract thinking, and problem solving skills. We know there are second and third order effects everywhere. There are just part of the non-idealities. However, we cannot talk about non-idealities without knowing how the circuit should behave ideally.
If you don't mind us asking, what additional info would've made the question clearer? We understand it can be frustrating when there's limited information. However, this is how interviews are usually conducted. However, we will try our best to incorporate your feedback in future content
@@HardwareNinja I think the device sizes is important and maybe even some hints on region of operation. None the less this a very interesting circuit. And please keep the questions coming. Dont let Bob stop you from doing good work. You are shaping so many young peoples careers.
Lol. You are clearly wrong. First of all we need to establish all devices are the same W/L. You could have spent 3 minutes on LTSpice to see why you are wrong. You could have breadboarded it in a half hour. Pay up a beer guys. Also, your video seems more smug and condescending. Both of you are at high points on the Dunning-Kruger curve, you are just at the beginning.
HI JP, Unfortunately you're so caught up on "being right" that you're missing the forest for the looking at the tree. Perhaps you haven't interviewed in a while or have forgotten how to do it. We're glad you're here to learn. 1. Interviews are all about ambiguity and lack of information. This is to evaluate how the candidate thinks and if seeks information. 2. When you know your foundations, and are good at them, you don't need a simulator to tell you how a circuit will work. Don't be a simulator monkey, don't be like Bob! 3. You cannot simply "breadboard" a circuit like this. It would be equivalent to say you could breadboard an OpAmp to prove it doesn't work (however, if you can let us know and WE will buy you that beer). These type of circuits are meant to be used on IC design, and work well with advanced process nodes. 4. We also saw your comment about the inverter. Again, don't get caught up on "being right". You're purposefully choosing to ignore certain things we have stated. Whenever you're explaining something you always assume idealities. The only reason to include 2nd or 3rd order effects are to probe deeper understanding or to actually build an IC. 5. Spend some time reading other people's comments and you'll realize it's a widely used circuit. Finally, if we said something that might have offended you during the video or the Reddit thread, we apologize. Our intention with this video is to highlight bad interviewers and help people realize sometimes it's not their fault. Hopefully interviewers are also watching these videos and learning. We, as engineers, tend to be very stubborn and prideful (as it should be). We should be able to recognize that we cannot possibly be right all the time though. Only by doing that we can hope to hire good candidates. Cheers!
Well, I don't love the way this guy goes through the circuits in the videos but he is right. If you are one of those designers that believe you are that good you can find this circuit in Vadim Ivanov's book on operational amplifiers(end of chapter 2). Also shown in E. Seevinck, “CMOS translinear circuits”. If you need more reference, Ivanov is a long time designer at TI that probably knows more about CMOS analog design and control theory than you think you know. Also probably holds more articles and patents than you.
@@matheuspimenta8486 Thank you so much for contributing to the content and being a part of the community! Please remember that we're not necessarily trying to educate people about IC design. The reason why you might dislike the way we present the circuit may be because we don't fully explain things but instead take shortcuts. However, that's the intent. We start with the assumption that our viewers have all the knowledge and tools to tackle the problems we present. Instead of education we just bring real life interview questions to expose our viewers to the problems.
@@matheuspimenta8486 You are right. There is a circuit at end of chapter 2 where it is clearly mentioned min selector circuit. However, another answer to the question could be a cascode current mirror (though matching won't be that good because of different VDS), but the output impedance would be high.
"Don't miss the forest for the tree". We believe we are all well versed on 2nd and 3rd order effects as well as non-idealities. Interviews, most of the time, are conducted assuming ideal devices. Finally, be sure to check out the paper in the description of the video. This circuit is widely used as a minimum current selector.
To be honest, I agree with "Bob" at some points:
The question doesn't mention any of the device size and device ratio which need us to make a lot assumptions. The device size and the actual current of I1/I2 affect the gate voltage of all of the transistor. For example, if I2
They were also very arrogant
Hi there, I really enjoyed this circuit, thanks! I think you got the main point, and I personally like calling the circuit a min(I1,I2) generator. However, for I1=I2, I think you should not say that "there is no minimum" (hear at 7:58s). Mathematically, the minimum between two equal values is the value itself. So, for I1=I2, min (I1,I2) = I1 = I2. In that specific case, the circuit produces I/2, a value which is not the minimum.
Hi!
Thank you so much for contributing to the discussion, we're glad you're here! Mathematically, this is absolutely correct. However, from a circuit perspective there's no minimum much like the inverter analogy. However, we appreciate the feedback and will work our best to be more concise next time. Thank you!
This is a fresh take on current mirrors! Love it! Never knew a selection function could be built by simple current mirrors. Also love the analogy too. It's amazing how you can come up with analogies on the fly. In an interview, I'd probably think of the inverter analogy only after it's over. Looking forward to more vids!
Hi Mohd,
Thank you so much for your feedback and for stopping by! Would it be fair to say that we earned that beer? :D
@@HardwareNinja I'd say definitely! But what do I know lol. I don't really have any experience under my belt.
I think the challenge of giving a mixed signal/analog interview is presenting devices in a configuration that the person being interviewed hasn't seen before so they can think out what happens, but still have it be simple enough so it is not a spaghetti mess. Solving a DC operating point of something and then asking something like "which device falls out of saturation first as the input increases" is totally fair and expected.
Working as Analog IC design engineer. Was present on the numerous interviews from both sides. Few comments:
1. Open ended questions without details. 100% something to expect during the interview. The additional questions that candidate asks will easily show his knowledge level.
2. I like the way of working out the interview problem that you showing in your videos. Doing analysis out loud, making assumptions and not just giving the answer or say “i don’tknow” - that certainly the right way to crack the interview.
3. I agree with “Bob” that you’re probably not really a specialist in analog ic design. You’re making a lot of silly mistakes and miswords. So I would not recommend to learn technical stuff from your videos, but rather learn the way of working and try to solve or read how to solve the problem on your own.
4. I bet no fresh graduate will go farther than “this is cascode current source circuit” and if sizing and currents are correct, cascode is working, else - not. Idea of minimum current selector is quite not trivial and without reading the papers about “feedback class ab output stages” papers or books or something simillar, i would not expect answers into the right direction.
5. I personally used such circuit in the real silicon, as a part of ab output stage. Works perfectly well, one of my favourite architectures now.
Hi Volodymry,
Thank you so much for your detailed feedback. We're glad to have you contribute to the discussion. Let us address some of your comments below:
1. Thank you, this is exactly what the aim of the content is.
2. See point 1 :)
3. Some of the team members have a career in analog design IC with plenty of experience. That being said, it is not our goal to teach anything related to design. That's why we don't focus so much on 2nd order effects or nonidealities before the ideal operation has been established. We operate from an assumption that folks watching our videos already have the technical know-how to answer some of the questions themselves.
4. We agree with you here! However, the point of an interview is to have the interviewee solve practical problems that they don't have much exposure to. That way we can really evaluate the degree of experience and problem solving skills that he or she may have.
5. We have implemented this architecture in SoCs as well. Hence, the reason we provided the question :)
In every analog circuits there is always room to dabate in everything.
Its not precise science if you do not take into consideration about everything.
Analog design is art and science in the same time.
Hovewer your explanations are based on intuition and common sense.
I understand where "Bob" is coming from. Not saying anyone is right or wrong, but depending on the biasing will totally change the way the circuit behaves...including different than the description in the discussion.
I just finished my degree and now I am doing my fist interviews so I really appreciate this content. Greets from Chile!!
How you arrive at your answer, the thought process, the assumptions and how you communicated those to your team mates are more important than being right. The best answer is arrived at when the team is in sync with each other. IC Design is a team play.
I thought the circuit presented was a current modulator i.e. I2 modulates I1. Varying I2 varies VDS1 and I1 will change slightly due to channel length modulation by VDS1. But i enjoyed listening to your thought process.
"if both are equal, then what is the minimum?" uhhhh min(x,x)=x
😁
Thank you so much for the sharing. In fact, this circuit is a well-known min. current selecting circuit. One can find a improved version using feedback control. See chapter 2 "operational amplifter speed and accuracy imrovement" by Vadim Ivanov, which is the best book for amplifer design.
This is just insane. It opened up so many pipes in my brain. I would love to be a regular visitor to this channel. Thanku team. Cheers
Thank you for the nice video!
One query:
When I2 > I1; Vgs of M4 is high. That's understandable. But,
"If I2 is high, source of M3 will be high" (Time stamp : 3:40) --- How you jump to this conclusion?
I think he's trying to say if I2 is high then the gate of M3 will be high, and that voltage is Vds2 + Vgs3, which will easily be high enough to keep M2 in saturation.
@@theabr4839 Does he not know that M3 & M4 are NMOS transistors? Because he got it flipped the other way as well on (time stamp 4:18). If M3 and M4 were PMOS, then his statement 3:40 and 4:18 is correct.
4:18 "The low vgs(m4) means source of M3 is low" ? I am confused because to draw less current(I2) shouldn't the source of M3 increase? Vg - Vs ---> lower Vs ---> higher I2 sounds incorrect. I think the source of M3 increases, Vg - Vs ---> higher Vs ---> lower I2 which is < I1. Help me on this.
Great content, thank you!
Loved the analysis without taking any higher order effects, it's simple and elegant. Of course, we need to be a bit flexible here to buy your answer, which is kind out of the box. Would never get to the min function selection without guidance. To be fair, this sounds like interviewer function to drive the answer to this direction. Expected answer would be the cascode current mirror with I2>I1 (assuming proper sizes), Then, the interviewer could ask: "what if I1>I2" and so on...
Bob failed miserably in understanding the "ideal" scenario. However, I think you should buy him a beer anyway, he seemed stressed.
Liked the inverter analogy to reinforce your point too.
This is a quite tricky problem and the complete answer is Iout= ( I1 .I2)/(I1+I2)( if we suppose that all the transistors are identical).Personally I will never test a candidate with a such problem.To be fair it is a trivial problem (for me ) but a real nightmare for most Analog designers to find the result that I have just provide.Also is quite odd what you say in the video you have just solved it either I1>>I2 or I2>>I1 and what you say when I1=I2=I we get Iout=I/2.Now the real questions are what is (are )the imperfection(s) and how to solve it (them)?
I agree Bob did lost perspective of it being an interview question and showed arrogance, but friend, your comments in the video are as arrogant as his. Please don't fall in the same game.
If you're assumption of ideal devices includes a zero knee voltage, then yes, this would be a min function. Transistor length be damned. Also, the ratio of the current mirrors, imo, is irrelevant. You can just set I1 and I2 to be I1' = A*I1 and I2' = B*I2 where A and B are the CM ratios and then let the CMs have a ratio of 1. Unless we change the problem in such a way that we now care about the currents going through the diode connected transistors.
When you do designs it is frequency matching.
Which subreddit is that? Looks entertaining.
Hi James,
Thanks a lot for stopping by! We decided to delete the thread to avoid people reaching out to Bob. You can find a copy of it in the description of the video.
What's your verdict? Beer for Bob or Beer for ByTor?
Bob was acting like a fool but he had a minor point about the case when I1=I2 (even though his analysis was a little off). Since you didn’t mention any hard specs his point could be valid. I’ve had my share of dealings with these old design guys, and they can be totally way off base sometimes, but then sometimes in reviews they can catch things you never thought of, so it’s a good idea to stay on their good side :)
I love the work that you guys do!
Thank you so much, Tom! It would really help us if you could give us a shoutout on your social media platforms, specially LinkedIn. :)
I understand that you are trying to make an inverter analogy for this case, but to be honest, I don't think it's fair to assume everything being "ideal" because *they simply don't exist in this world*. In your inverter analogy, if the inverter isn't ideal, the output would give logic 0 for 50% of the time and logic 1 for the other half of the time, which is still functioning as inverters, except now you are inverting random noises. Actually you can use this distribution to figure out the skew of the inverter and so on, but that's a whole other topic. But the point was that, even in the case when your input is vdd/2, inverters still "inverts" a signal.
Whereas in this example, if I1=I2, and you still wanted to maintain the min(), you can't just say it is okay to output I/2, because min(I1,I2) is not equal to half of each quantity either. You have to put an asterisk in the case when you assume I1=I2 to say that min() does not hold or something. For example, mathematically speaking, min(10,10) can never equal to 5. And that's entirely okay.
A better argument imo would be to say that even if you assume I1=I2, when these transistors are on *real* chips, process variation will make sure they are almost never equal, and so the min() will still hold in those cases.
Hi,
Thank you so much for your comment, we're glad you're here! We would like to address your comment about non-idealities. You're correct, nothing in this world is ideal. However,, during interviews, 2nd and 3rd order effects are not talked about much (unless it's a position for a role that requires a lot of experience). The reason for this is that if candidates cannot infer how a circuit will behave ideally, then it's likely they don't understand the 2nd order effects either.
The same analogy can be done with an amplifier. If it's biased correctly, then it works as an amplifier. If there's a step and it stops slewing or are close to the max/min swing of the amplifier it will behave non-linearly. Just because of that, it doesn't make it any less of an amplifier. We do appreciate your feedback very much though and will use it to make our future content better.
The fact they said vdd/2 is telling. Even in digital, let alone in analog, they should know pmos and nmos are different and why the "middle" voltage isn't vdd/2. (Though you could modify W/L_n and W/L_p ratios). (But again, you'd think they'd have basic concept of process corners, etc especially to be lecturing experienced analog guy comments online.
All W/L on tape out IC😅
I see it all p+N w/L on the ic
When you do design and it needs be matched on frequency, (N+P all C effect )
need more please !
The circuit is interesting once one reads how it's used in a class-AB amplifier. However, the way it's presented here is too simplistic and lacks key details such as sizing.
Finally, I don't think it's a minimum current selector like the way you present it. If I2 > I1, for example, M3 sure wouldn't carry I2 as its source is on higher potential than that of M4, but there's no guarantee that M2 would be able to carry I1 either as its drain potential would be lower than that of M1 and Ids isn't constant after Vds > Vdsat.
Thank you so much for the feedback and contributing to the discussion. Details, like sizing, tend to become irrelevant in an interview discussion as we're not designing anything. Instead the interviewer is after problem solving and how one can use fundamental concepts to decipher what the circuit is doing. Remember we're not trying to teach anything new nor are here to educate people about core concepts. Instead we're bringing real life interview questions to you and assume you have all the tools to solve the problem.
Everyone can have Bob tendencies... I looked at the mirror circuit and initially concluded a current controlled current mirror. I was reasonably sure but enjoyed the answer and detail.
Thank you so much for your comment and contributing to the discussion! We're not looking for everyone to agree with our answers, after all they're open ended questions. What we wanted to showcase, as you rightfully point out, is that some engineers can get stuck and caught up on things.
Thank you for the video👍
We're happy to help and that you're here!
Good paper but it would be very difficult to know that this is a minimum current selector. Too many assumptions here.
Hi Yunus,
Thank you so much for contributing to the discussion! Could you elaborate what you mean by "many assumptions". We love feedback and would really like to understand how we can provide a better service to the community.
Also, let's not forget the main point of interviews that is knowledge of basics, abstract thinking, and problem solving skills. We know there are second and third order effects everywhere. There are just part of the non-idealities. However, we cannot talk about non-idealities without knowing how the circuit should behave ideally.
@@HardwareNinja you make too many assumptions. Maybe you have to provide more info with questions. Bob seems to have a point (little bit)
If you don't mind us asking, what additional info would've made the question clearer? We understand it can be frustrating when there's limited information. However, this is how interviews are usually conducted. However, we will try our best to incorporate your feedback in future content
@@HardwareNinja I think the device sizes is important and maybe even some hints on region of operation. None the less this a very interesting circuit.
And please keep the questions coming. Dont let Bob stop you from doing good work. You are shaping so many young peoples careers.
@@yunusdification Thank you so much for the kind words! We will take your feedback into account on our future content.
source degeneration circuit?
Lol. You are clearly wrong. First of all we need to establish all devices are the same W/L. You could have spent 3 minutes on LTSpice to see why you are wrong. You could have breadboarded it in a half hour. Pay up a beer guys.
Also, your video seems more smug and condescending. Both of you are at high points on the Dunning-Kruger curve, you are just at the beginning.
HI JP,
Unfortunately you're so caught up on "being right" that you're missing the forest for the looking at the tree. Perhaps you haven't interviewed in a while or have forgotten how to do it. We're glad you're here to learn.
1. Interviews are all about ambiguity and lack of information. This is to evaluate how the candidate thinks and if seeks information.
2. When you know your foundations, and are good at them, you don't need a simulator to tell you how a circuit will work. Don't be a simulator monkey, don't be like Bob!
3. You cannot simply "breadboard" a circuit like this. It would be equivalent to say you could breadboard an OpAmp to prove it doesn't work (however, if you can let us know and WE will buy you that beer). These type of circuits are meant to be used on IC design, and work well with advanced process nodes.
4. We also saw your comment about the inverter. Again, don't get caught up on "being right". You're purposefully choosing to ignore certain things we have stated. Whenever you're explaining something you always assume idealities. The only reason to include 2nd or 3rd order effects are to probe deeper understanding or to actually build an IC.
5. Spend some time reading other people's comments and you'll realize it's a widely used circuit.
Finally, if we said something that might have offended you during the video or the Reddit thread, we apologize. Our intention with this video is to highlight bad interviewers and help people realize sometimes it's not their fault. Hopefully interviewers are also watching these videos and learning. We, as engineers, tend to be very stubborn and prideful (as it should be). We should be able to recognize that we cannot possibly be right all the time though. Only by doing that we can hope to hire good candidates.
Cheers!
Well, I don't love the way this guy goes through the circuits in the videos but he is right.
If you are one of those designers that believe you are that good you can find this circuit in Vadim Ivanov's book on operational amplifiers(end of chapter 2). Also shown in E. Seevinck, “CMOS translinear circuits”.
If you need more reference, Ivanov is a long time designer at TI that probably knows more about CMOS analog design and control theory than you think you know. Also probably holds more articles and patents than you.
@@matheuspimenta8486 Thank you so much for contributing to the content and being a part of the community! Please remember that we're not necessarily trying to educate people about IC design. The reason why you might dislike the way we present the circuit may be because we don't fully explain things but instead take shortcuts. However, that's the intent. We start with the assumption that our viewers have all the knowledge and tools to tackle the problems we present. Instead of education we just bring real life interview questions to expose our viewers to the problems.
@@HardwareNinja Sorry if I was not clear but meant that your explanation is correct and giving references to support that.
@@matheuspimenta8486 You are right. There is a circuit at end of chapter 2 where it is clearly mentioned min selector circuit.
However, another answer to the question could be a cascode current mirror (though matching won't be that good because of different VDS), but the output impedance would be high.