Just a question - at 27:50. The only connection Q0 has to the rest of the circuit is via the first AND gate right. now if Q0 were to be a 1 or a 0, that AND gate still wouldn't produce a one (therefor toggling the next JK) because NOT-Q3 is still 0... How does the "toggle command" move onto the next JK? excuse me if i missed something stupid :) And thanks so much for the videos - better than my lectures!! haha
Technically, it does work without the AND gate between the first two flip-flops. However, for the sake of clarity, the AND gate is a good idea.
What's with the "delay"? Does it HAVE to be there?
Thanks for uploading your videos. You make it seem soooo easy!
woah! This is great, never saw it explained so intuitively!
I'd like to see videos of your lab projects because you would be using pulldown resistors and stuff that you don't see on all your videos.
love, ty sooo much!
Actually, without an AND gate between flip-flop 1 and flip-flop 2, only the first output actually happens.
Great video thanks
It isn't in toggle mode since there is no such thing with a JK flip-flop.
can u do a video of it including both CLK and PRE?
instead of taking and of q0 and q1 cant i just use q1 to give to j and k
What software are you using for illustration?
Just a question - at 27:50. The only connection Q0 has to the rest of the circuit is via the first AND gate right. now if Q0 were to be a 1 or a 0, that AND gate still wouldn't produce a one (therefor toggling the next JK) because NOT-Q3 is still 0... How does the "toggle command" move onto the next JK? excuse me if i missed something stupid :)
And thanks so much for the videos - better than my lectures!! haha
why dont you just connect the q output to the clock input?
He's talking about Synchronous Counters, each clock input should depend on the clock signal not on the Q output.
i like this vedio
love, ty sooo much!