Do You Know How Signal Travels Through a VIA? Are You Sure? | Explained by Eric Bogatin
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- Опубликовано: 9 июн 2024
- What is happening with signals when tracks are changing layers in PCB? Thank you very much Eric.
Links:
- Ansys free version: www.ansys.com/academic/studen...
- Ten Signal Integrity Rules of Thumb webinar: www.signalintegrityjournal.co...
- FEDEVEL courses: courses.fedevel.com/
Chapters:
00:00 The board
02:02 How signal travels through a via
04:32 About setup
07:26 About ground
10:38 With GND VIAs
13:45 Current, plane, skin effect
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- Robert 
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What other simulations would you like to see?
Thanks Robert - how about showing the same simulation for differential microstrip and differential stripline .
@@chromatec4311 I was going to ask the same thing. I'd be interested to know the results for differerential pairs with one single via instead of two, because sometimes I just have room to place one single via only for the pair.
Would adding a capacitor to link the two planes, instead of vias, be effective, so they can be at different potentials?
@@Gelf54 I think the problem with capacitors is that their impedance varies with frequency making them less effective. But you raise a good point because the via linking the return planes is also an inductor at high frequencies - this is why its good to add several of them.
Hello Robert,
Please ask from Eric a simulation of Common Mode conversion and it's impact on EMI/EMC.
This changes how I do my PCB layout from now on. Please show more practical simulations like this. These are great!
During an interview,I spoke about transfer via,the guy didn't know what it is,eventhough he designed fpga boards
It’s pretty normal bro. When you’re designing 15-20 pages of schematics and also routing the board, the amount of details you know goes down.
Managers don’t understand this
@@AcctistaZ I don't understand your point
Wow this was an excellent presentation, I could listen to Eric lecture all day. I've been thinking of the E-field all wrong, not realizing it would spread throughout the cavity I thought I was clever for using a single return via this whole time. After seeing the results of the field solver demonstration it's evident that I need to start using multiple return vias around the signal via. Outstanding! Love it when I learn something. Thanks Robert!
Hi. A lot of thanks for this presentation. I have few questions:
1) How about distance between VIA for signal and Return VIAs. How short distance I need to use between them?
2) How about simulation just for 1-2Mhz because for small IoT device not using 10Ghz.
A lot of thanks for Robert and Eric. Both of you doing great job in our industry.
YAY! A short video to watch immediately! Thanks a lot for sharing. Now its watch time!
Really interesting video
very great video! Thank you!
Today is the webinar I must find it!
Very interesting, thanks.
Very educational look at a single via and return structure. I would love to see the same level of detail for a decoupling capacitor, or how much worse the single via simulation looks when the two planes are at different potentials and are capacitively coupled...
Two questions come to mind when watching this video:
1. Are the return vias only internal between the return planes (layers 2 and 3) or do they go through all layers?
2. What about boards with 8 or 10 layers, how does the stackup work?
Great Video as usual 👍. Would be great to have the source files so we could try the simulation ourselfes.
Hi! Are these Vias different from the ones which we use in antenna designs to to short the radiating element and ground? Like PIFA antenna?
Cool, I like that kind of simulations. Would it be possible to see the energy that is radiated into space?
Hey can you design a usb c hub? Been wondering how they work.
Could you say, because extra via’s don’t really add up on the cost ladder, just use a return via for all signal via’s? Slow and fast?
I mean: because most signals are block signals with a lot of harmonics
theoretically yes, practically it could make routing / placement not optimal especially because VIAs take a lot of space. So it may not be necessary to overdoit.
Which simulation tools are used? Can OpenEMS be used for this? I'm a broke engineer.
This content is great. I appreciate the shorter videos.
I don't understand why Sugnal gnd gnd signal offers the possibility to add transfer vias and not gnd signal signal gnd
Look on board where is many components on top and bottom layer and these layers also are GND. It will be all in holes. But if GND in inner layer you will have good polygon without any gaps.
It's all connected by capacitance and only dc is not going through.
Swagggg
Great video that has way too much commentary…. This message could have been easily explained in 5m instead of 15m.