To understand why J2 is reverse bias we need to go back to the basics. Voltage is the difference of higher potential to the lower potential, so in this case C's higher potential is Vee+ not Vbb- and lower potential is Vbb+ hence J2 is reverse bias.
According to circuit Vbb's +ve terminal is connected to p side and -ve terminal is connected to n side. So, Vbb will maintain a higher potential at p side and lower potential at n side. So, irrespective of other parts of circuit collecter base junction is forward biased.
If u feel like CB junction is Forward Biased then just draw transistor in form of two diodes connected back to back just beside NPN & u feeling will go 🙂
I think that ground is a problem if it were not present then the biasing will be appropriate only thing to be done is applying greater EC voltage than Vbc
Thanks a lot for your series lecture. Here the CC figure is correct in accordance with KCL Ie=Ib+Ic. But can you please explain how CB junction is in reverse biased? And I think there is a mistake of your KVL. It should be Vce=Vcb+Vbe.
Vee(5V)>Vbb(1V), so CB junction is reversed biased. The *direction* of voltage difference (Vee-Vbb) is opposite to the *direction* of CB barrier potential. In general, follow this (conventional current flow) convention for npn transistor, Ie(*outgoing* current to *negative terminal* of battery) = Ib(*ingoing* current from *positive terminal* of battery) + Ic(*ingoing* current from *positive terminal* of battery)
Base terminal= +ve voltage , and collector terminal =+ve volatage . To make collector base junction reverse bias , VEE > VBB . VEE is more +ve than VBB.
How come the BE and BC junctions are respectively FB and RB? For me they are both FB when I look at the voltage sources (Vbb has the + terminal on the P side so FB and Vee has the - terminal on the n side so FB)... Can someone explain?
i prefer you see it with respect to output circuit and you will find the same j2 being reverse biased( Yes,the j2 is forward biased if your perspective is from input it is allowing the current to rotate in the left loop which being acted as a opposer that is reverse biased when you look it at the right loop perspective...correct me if i'm wrong guys.
In common collector transistor, the collector and the emitter both are biased in the right junction by V(EE), negative part of V(EE) biased emitter forwardly and the positive part of V(EE) biased collector reversely.
Yes. I am also confused, bcz input side CB junction is in reverse biased and output side EB junction is forward biased! How come FB output chara of CC configuration equal to RB output chara of CE configuration. Totally confused
Correct me if I am wrong... his diagram is correct... For J1 to be forward biased E is to be connected to -ve terminal and B to + ve... J2 matches automatically
Sir, collector base junction should be reverse biased but here you have shown that base is at a potential higher than the collector...that means collector base junction is forward biased..please edify
Input volatge should be Vcb, and not Vbc . Vbc means Base is at higher potential than Collector, which means this makes it forward biased. This is what you explained about the subscripts in the starting videos that we write higher potential one before. 🤔🤔🤷
P region pe positive voltage hai let suppose it is 2volt Jo ki input voltage hai ie Vbc =2V ..now collector region Jo ki n type hai uspe bhi positive voltage hai but ispe more positive voltage hai than base region Jo ki output voltage hai let suppose 5 volt ..to overall voltage at collector will be 5-2=3 which is more than p region so junction CB will come to be in reverse bise
At 2.30 you write collector current Ic equals alpha times emitter current Ie. At 4.07 you write collector current Ic equals alpha times emitter current Ie plus Icbo. Mathematically, these two equations cannot be correct at the same time. Would you kindly explain what is Icbo?
Equation will be held true for all configurations but alpha value will change. Edit: In common emitter configuration video, if alpha value range stayed 0.95-0.98, then we'd get beta range of 19 to 49....but beta value ranging from 50 to 400. I hope you get what I'm trying to convey. Cheers.😁
Because if Vee > Vbb , then collector goes to a higher potential than base , even though both are positive, and so ultimately it becomes reverse biased. Condition is Vee has to be larger than Vbb for collector to be reverse biased.
We can see and tell the amplification is only in the active region. But if we see the graph of the output characteristics of the common emitter than in the saturation region the current Ic is increasing but not in the way like active region but still it is increasing so can't we say that in saturation region the signal is amplified to some extent.
how u said that reverse biased for collector w.r.t.base because n-type layer is connected negative terminal and p-type layer is connected to positive terminal then how u told that is reverse biased
The diagram is really wrong and I have verified it using simulation. The base collector junction is not really reversed biased. The wrong diagram is used in many places, but it is wrong.
Can you please send a reference for a correct diagram, I was also thinking this diagram was wrong, but on many place on internet ,the same diagram is used and now I am confused.
This is a GP saver mehn. You teach way better than most lecturers. My lecturer even skipped the transistor topic entirely. 🤧
Dear speaker and Neso academy, your efforts are really commendable.
Sir i am from NIT and u are teaching better than my professors wuo hace 30 years of experience
To understand why J2 is reverse bias we need to go back to the basics. Voltage is the difference of higher potential to the lower potential, so in this case C's higher potential is Vee+ not Vbb- and lower potential is Vbb+ hence J2 is reverse bias.
According to circuit Vbb's +ve terminal is connected to p side and -ve terminal is connected to n side. So, Vbb will maintain a higher potential at p side and lower potential at n side.
So, irrespective of other parts of circuit collecter base junction is forward biased.
KVL says otherwise
sir according to figure collector base junction is not reverse biased
Actually it is R.B...see it again..
Yes in reverse bias p should be connected with negative
@@dheerajkumarsingh5789 can you explain that? I don't get it :/
@@dheerajkumarsingh5789 explain please
@@dheerajkumarsingh5789 actually you are the one that need to see it again!
i am from IIT and you are teaching better than our professor.........
Chal jutha kuchh bhi bolta he🙄
@@itsmrunknownky jhut bhai ?
If u feel like CB junction is Forward Biased then just draw transistor in form of two diodes connected back to back just beside NPN & u feeling will go 🙂
Thanks a lot, u saved my time 😮
Ca u add a picture
sir, kindly explain the reverse biasing of base and collector junction properly
I think that ground is a problem if it were not present then the biasing will be appropriate only thing to be done is applying greater EC voltage than Vbc
Thanks a lot for your series lecture. Here the CC figure is correct in accordance with KCL Ie=Ib+Ic. But can you please explain how CB junction is in reverse biased? And I think there is a mistake of your KVL. It should be Vce=Vcb+Vbe.
i think it is because, they are in active mode
sir in this video you say collector and base junction is reverse bias but it is not please check
I agree. The C-B junction is in forward bias. Isn't it wrong?
Ya..this is also my query...
Vee(5V)>Vbb(1V), so CB junction is reversed biased.
The *direction* of voltage difference (Vee-Vbb) is opposite to the *direction* of CB barrier potential.
In general, follow this (conventional current flow) convention for npn transistor,
Ie(*outgoing* current to *negative terminal* of battery) = Ib(*ingoing* current from *positive terminal* of battery) + Ic(*ingoing* current from *positive terminal* of battery)
udeep shrestha sorry bro i didn' t get it what you are
trying to understand
Base terminal= +ve voltage , and collector terminal =+ve volatage . To make collector base junction reverse bias , VEE > VBB . VEE is more +ve than VBB.
I love you soooo much like my mother, you explain every thing simply
How come the BE and BC junctions are respectively FB and RB? For me they are both FB when I look at the voltage sources (Vbb has the + terminal on the P side so FB and Vee has the - terminal on the n side so FB)... Can someone explain?
I am happy many people are confused there :D
The thing is input side is always Fb and output is rb
Its not about the junction
@@pratikas2589 why then did he say that emitter base junction is forward biased? This is a huge error
Sir as you said,the collector junction should be reverse biased..but in the above concept why is it forward biased🙄
Vbb != Vbe .. so additional voltage source will reverse bias the Transistor ..
i prefer you see it with respect to output circuit and you will find the same j2 being reverse biased( Yes,the j2 is forward biased if your perspective is from input it is allowing the current to rotate in the left loop which being acted as a opposer that is reverse biased when you look it at the right loop perspective...correct me if i'm wrong guys.
Same question goes from my side
please upload power amplifier trasistor and its types class A, B AB C
Your videos and lecture are very useful to me for clear understanding.Thank You Sir.
In common collector transistor, the collector and the emitter both are biased in the right junction by V(EE), negative part of V(EE) biased emitter forwardly and the positive part of V(EE) biased collector reversely.
Sir can you explain the input characteristics of the common -collector configuration
Yes. I am also confused, bcz input side CB junction is in reverse biased and output side EB junction is forward biased! How come FB output chara of CC configuration equal to RB output chara of CE configuration. Totally confused
Thank you sir ❤️
Correct me if I am wrong... his diagram is correct... For J1 to be forward biased E is to be connected to -ve terminal and B to + ve... J2 matches automatically
Sir, collector base junction should be reverse biased but here you have shown that base is at a potential higher than the collector...that means collector base junction is forward biased..please edify
his diagram is correct... For J1 to be forward biased E is to be connected to -ve terminal and B to + ve... J2 matches automatically
By selecting value of Vee greater than Vbb reverse bias of cb junction is achieved and eb junction is always forward biases in given fig..
Input volatge should be Vcb, and not Vbc . Vbc means Base is at higher potential than Collector, which means this makes it forward biased. This is what you explained about the subscripts in the starting videos that we write higher potential one before. 🤔🤔🤷
Can you explain how forward and reverse bias form in cc configuration
It's not quite clear to me either. Because I thought the emitter base region is always forward biased. His circuit configuration doesn't satisfy this
P region pe positive voltage hai let suppose it is 2volt Jo ki input voltage hai ie Vbc =2V ..now collector region Jo ki n type hai uspe bhi positive voltage hai but ispe more positive voltage hai than base region Jo ki output voltage hai let suppose 5 volt ..to overall voltage at collector will be 5-2=3 which is more than p region so junction CB will come to be in reverse bise
sir can u give the common collector input characteristics lectures
sir Vcb is connected in forward bias because +ve side is connected with p type sir
0:41 "Collector-base junction is reverse biased" Are you serious? Vbb is forward biasing the junction.
Bro Vbb ki polarity galat h change Karo Ans mil jayega
thank you sir
Sir please tell why cc configuration not used as a amplifier ?
Thank you sir , But if u can described about pnp transistor it will help for me
Why we consider emitter base junction and collector base junction,why we didn't consider emitter collector junction and base collector junction ?
Sir Can i have common collector output characteristics graph with explainations?
I also need it
please explain the biasing technique b/w junction....
Good to understand
At 2.30 you write collector current Ic equals alpha times emitter current Ie. At 4.07 you write collector current Ic equals alpha times emitter current Ie plus Icbo. Mathematically, these two equations cannot be correct at the same time. Would you kindly explain what is Icbo?
Icbo is very small and he neglected it at first. Icbo is the reverse saturation current in common base measured when emitter is open circuited.
Bro could please upload a video lecture on Bayes theorem
And Bernoullis trails
how will you prove your second equation at 4:28. i thought that equation was only for common base configuration
Equation will be held true for all configurations but alpha value will change.
Edit: In common emitter configuration video, if alpha value range stayed 0.95-0.98, then we'd get beta range of 19 to 49....but beta value ranging from 50 to 400. I hope you get what I'm trying to convey. Cheers.😁
in a transistor the EB junction should always be FB & the CB should be RB...that's what i knew!!
2:11 this is not in active condition it is in saturation condition
I think your transistor is working in saturation region.
I think so
He said crt, but wrote wrong
logically emitter is always forward biased and collector is always reverse biased with respect to base but in this CC config is not like that why?
krish Bala Input terminal should me F.B n o/p reverse
Because if Vee > Vbb , then collector goes to a higher potential than base , even though both are positive, and so ultimately it becomes reverse biased. Condition is Vee has to be larger than Vbb for collector to be reverse biased.
can i write Iceo instead of Icbo/(1-∝) at 5:35
Thank you sir..
Is that correct the direction of the Vbb🤔
sir can you explan common collector input charactristics plz jazakallah for all videos you made complicated things easy
Cb have to reverse biased but you do it in forward
how is the CB junction reversed biased as p of base is connected to positive and n of collector is connected to negative of the battery?
very nice
Biasing in cc configuration is entirely different from that of CB and CE many students are asking about it .Why are you not replying???
I think he don't know
Sir dont we have input and output characteristics for common collecter configuration?
sir plz provide all leacture on MICROPROSSOR for Btech student
TECH 25000V 😐
ThankYou ThankYou
how to weather the trasister is in active mode or in saturation state
Excuse me ... Jn CB is forward biased here
sir what about input characteristics?
Sir here isn't the collector forward biased. But u told that collector should be reverse bias
We can see and tell the amplification is only in the active region. But if we see the graph of the output characteristics of the common emitter than in the saturation region the current Ic is increasing but not in the way like active region but still it is increasing so can't we say that in saturation region the signal is amplified to some extent.
Absolutely right
There is problem in this video about the biasing... Many people are confused ... Please reply about this.
where can we find these notes?
All have same question , pls answer this.
Think u Sir
👍👍
how u said that reverse biased for collector w.r.t.base because n-type layer is connected negative terminal and p-type layer is connected to positive terminal then how u told that is reverse biased
sir ,you didn't show the input characteristic of common collector !
Why it is V ee it should be V cc...... Right?
input characteristics kahan hyn is k?
The collector base junction is forward biased I think it should be reverse biased
Please never take ECE.
These semiconductors are real pain.
Where is input characteristics
There is something wrong in the biasing i think..
Sir in this video you are not clearly mentioned I have a doubt on this
Sir comic-sans mat use karo plz
Please 😫🙏🙏💓clear it
Sir give proper reson who base collector is reves biased
Can’t we neglect I CBO
But here both are forward biased
The diagram is really wrong and I have verified it using simulation. The base collector junction is not really reversed biased.
The wrong diagram is used in many places, but it is wrong.
Can you please send a reference for a correct diagram, I was also thinking this diagram was wrong, but on many place on internet ,the same diagram is used and now I am confused.
sa akong classmate sa 134, huhuhy wala japun ko kasabot
sir plzz hindi me bnaya kro video plzz sirr