JFET: Construction and Working Explained
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- Опубликовано: 19 июн 2024
- In this video, the construction and working of n-channel JFET and p-channel JFET are explained.
By watching this video, you will learn the following topics:
1:01 Construction of n-channel JFET
2:25 Working of n-channel JFET
6:01 Output characteristics (Drain curves) of n-channel JFET
11:07 Different regions of operation of JFET
13:07 p-channel JFET
14:44 Symbols of n-channel and p-channel JFET
JFET (Junction Field Effect Transistor) :
The junction field Effect Transistor (JFET) is used in a wide range of applications. It is a three terminal device. (The 3 terminals are Gate, Drain, and Source)
JFET can be classified as either n-channel JFET or p-channel JFET.
n-channel JFET:
In the n-channel JFET, the channel is made up of n-type semiconductor material and two small p-type regions are formed near the channel.
p-channel JFET:
In the p-channel JFET, the channel is made up of p-type semiconductor material and two small n-type regions are formed near the channel.
In this video, the construction and working of JFET are explained by taking the example of n-channel JFET. And at the latter part of the video, the output characteristics (Drain curves) and the different region of operation of JFET is also discussed.
Different regions of operation of JFET:
1) Ohmic region
2) Saturation Region
3) Cut-off Region
4) Breakdown Region
This video will be helpful to all students of science and engineering in understanding the construction and working of JFET.
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#PchannelJFET
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The timestamps for the different topics covered in the video:
1:01 Construction of n-channel JFET
2:25 Working of n-channel JFET
6:01 Output characteristics (Drain curves) of n-channel JFET
11:07 Different regions of operation of JFET
13:07 p-channel JFET
14:44 Symbols of n-channel and p-channel JFET
Nice explanation in video as well as sequential informed in comment as well ....Thank u...😇😇👍
Please give short note in page so we can study easily
Give notes it may be good
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@Rey Cassius instablaster ;)
Tomorrow is my sem exam and today I am watching........
One month later I am in the same predicament bro, I have exam tomorrow 🥲
Me too
Did you pass in the exam
Me too
me too broo
amazing lecture. even better than my prof at IITM
Ohh!
Really?
nice video!!!
at pinch off voltage, 2 depletion region nearly touch each other, but don't touch it due to electro-static repulsion...
Your teaching is really great! The main thing I like about your videos is the color theme! The color theme is really well thought and really makes you stand out! Thank you soo much sir!
your lectures are so good,easy to understand,covers all the basics concepts as well as important points that i doubt one could find a better channel for electronics than this. i always feel like I'm in class while watching your lectures. Thanks a lot sir !
this is one of , if not the clearest explaination of a jfet i've come across
I used it in my circuits on my channel. Thank you for sharing!
This channel gives the crct explanation on all the theories and concpets...gives much clarity on the subject..tq for this channel members...available the more and more videos on differnet concepts with different expalnations
Sir No words for you .... You are great... Thanks a lot... It helped me to understand my project related to JFET.
Simple yet very easy to understand. Bravo sir ! You did gr8 😊
Clear explanation
Every video of yours is really helpful and really easy to understand.
The way of explaination is awesome sir👍
You have helped me a lot for electronics. Thank you so much.
Dhanyawad sir bhut accha padhaya apne
You're very very better than my teacher sir ❤❤❤ Clear and clear explanation 🤩🤩
Thankyou sir, you literally saved my 15 marks, may god bless you sir❤🙏
Awesome sir🙏🙏👏👏👏 ............may god bless u ........ thanks for sharing your knowledge to us 😊🙏🙏
Great explanation. Cleared my doubts. 🙏
Wonder job sir...👍. It is very well explained. Thanks for your work sir.
excellent work bro. thank bro for not displaying ads.
Very very thanks bro it's awesome to understand😁
Best explanation!!Thank you very much sir
I would personally suggest that this is the bestest video on youtube for explaining the concept of JFET.....really impressed brohh...
Thank you a lot. Very clear explanation
excellent explanation makes the topic clear ..
Thanks for creating such types of lecture
Excellent lecture sir..
Keep uploading more videos regarding Electronics..
谢谢，很好的解释！
awesome explanation ,thanks and keep it up bro.
Kya explained sir.super .keey it up .may god bless you.
Excellent explain sir .
I'm first year ece 2021 corona batch
So classes are running online I didn't understand online classes so I'm came here
thank you.... very helpful
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Clear explanation tnk u
your videos will make us pass in end semester exams .
Very good explanation ❤
Very nice video.thank you...
Thank you so much!
Very nice and cool explanation.
Very good explanation sir thank you sir🙏🙏
Tq you giving an information for the jfet.
good explanation thank you
I have my sem exam tomorrow and i am learning now
thanks you are awesome
very clear explanation
Nice useful for ...E.E.T..students
thanks a lotttt, make sense :3
Love you!
Very good 👍
Thank you so much
Sir u r great......
Thank you sir 😊
thanks a lot!
Thank you so much sir
@12:10 You had put that when Vgs is greater than or equal to Vp the device has 0 drain current. I think you had meant to type when Vgs is less than or equal to Vp, the device has 0 drain current and is in the cut off region
Thank you.....
Awesome explain👍
Simple, complete narration of topic.
I am a Master degree student.
What happened if one reversed the polarity of V (ds)?
In some JFET, drain and source terminals are symmetrical. So, if you interchange them it will work fine. (only the direction of current changes accordingly). But it's not allowed in all JFETs I think. Theoretically, it should work fine.
You are copied from neso academy
Really Amazing video but please also provide notes it would be really helpful for students
Thank you sir
Great sir thanks a lot
Sir , there is a confusion for me , please be kind enough to see the Motorola data sheet for BFW 10 JFET . Are the pin outs labeled correctly? (Pin 2 with the arrow head is labeled as drain). Your reply is much appreciated.
Nice explanation sir
What software do you use to design these circuits? Thanks
Thanks to indian teacher who made these soo simple
JFET video is very useful
Super explanation sir
Best video ever for next day exam 😅
Amazing lecture better than MIT
i usually love your videos but i feel that different widths of depletion region, starting at 4:25, could have been explained better.
Clear 🎉🎉👍👍
God bless
Thankyou
🤩🤩🤩
The tap-water analogy is a little confusing because you have the flow in reverse in comparison to the FET.
But you can still think of a water-analogy:
Imagine you sitting in your bathtub, and you have a lever (gate) that controls if the water should be drained. When you
pull the lever, the water starts going into the drain, and somewhere down the pipe there will be the "source" where it flows out again, into the canalization.
Of course, if we choose to think of physically-correct current instead of conventional current, then the tap-analogy in this video is correct.
Vry great sir
Nice sir
can you please tell me which software you have used to write all these things. Also, the type of the stylus pen and the writing pad you have used. Please tell me. I want to buy for my research purpose..
You can do this using adobe illustrator, or simply ms paint. apple pen will be the best to go with
sir make videos on analog and digital communication,
waah maza aa gaya
bas marks aane chahiye
what if we +ve supply VGS for n channel instead of -ve supply. Will current increase??
can we interchange source and drain terminals?? if changed what happens.
While working of n channel,,u r telling reverse saturation voltage increases then depletion region increases. But in bjt explanation, told depletion region decreases. Plz give me clarification
sir, should
the DEPLETION region in the "p" channel
should be opposite of the "n" channel?
(in case of shape?)
Explain the working of p channel jfet with neat circuit diagram with cases..?
Yes plz
So JFETs (both N-Channel and P-Channel) are depletion mode only, allowing current to pass when Vgs = 0
For N-channel (negative Vgs = -Vp , will turn current off)
but cant understand the current direction through gate side at the end for both p and n type jfets
U said arrow indicates the direction of flow of current when pn junction is forward biased but actually it is reversed biased right? Then only depletion region is widened.
I have a doubt if the pn junction in it is reverse biased then the depletion region decreases and it increases the width of channel present between, so the current Id must rise but it decreases as the gate is made more and more negative and the width is increased....???? So...
Its other way around actually. In pn junction, as the reverse bias increases, the width of the depletion region increases.
When Vds is applied and being the two pn junction at reverse bias,initially maximum current will flow and as we increase Vds current will reduce ,so very small current due to minority carrier will cause reverse saturation current from source to drain ,but eventually when pinch off occurs current becomes constant so no more current actual gets added up ,it's just minority carrier with enough thermal energy under an applied field enters into the drain..
When Vds is more than pinch off voltage Vp then both the depletion regions touch each other so the current flow is minimum so why is it itself the maximum current through it?
The thing is, when the Vds is less, then fewer electrons are pumped into the channel (Considering n -channel). As, Vds increases, more electrons are injected into the channel. That means as we increase the voltage Vds, the current increases. But it can happen only up to pinch-off voltage. After that, the drain current gets saturated. So, that's the maximum current.
I hope it will clear your doubt.
💙💙💙💙
At 9:52 I don't understand if Vgs is positive or negative at the gate :// and also it's not clear how Vgs is connected looking at the wires. Thanks.
sir you've talked wrong about cutoff voltage, you have said both pinch off and this are same, which is not....
12:58 also, positive bias(Vgs > 0) is not applied in JFET because it will cause damage/burn due to very high current
12:09 you mean Vgs
Yes, correct.. applying positive bias to JFET will lead to flow a reverse input current through gate which will eventually increase with increase in +Vgs.
Sir in n channel jfet is possible to apply gate voltage postive.is the characteristics would change?????
For n channel JFET, it is not advisable to apply positive Vgs. It may damage the JFET. The gate voltage may be positive but Vgs should be less than 0.
Sir, you said that at the time of pinch off the Id current should become zero, but if it becomes zero then the depletion layer gets removed, and the different potential levels across n channel are also removed. So the current technically never becomes zero.
Because as far as i know, Depletion layer is controlled by reverse bias voltage not current.
So why does the depletion layer recede when the current (hypothetically) becomes zero?
Please shed light on this matter...
7:45 onwards, that is what I have explained.
Nice explanation sir, can you kindly tell me is there any pinch off towards source when Vgs is applied. or how Id becomes zero exactly at Vp. Thank you sir.