How to create a custom PYNQ overlay

[@rohankalbag5541]

Very helpful and intuitive explanation, thanks a lot

[@europeanunion5765]

11:10 it seems you need the .hwh file as adder.hwh from the hw_handoff subfolder next to the bitstream file on your pynq, otherwise the pynq will show an error message that it cannot locate the bitstream

[@陳立勝-z3i]

after generate bitstream, File>Export>Export Hardware then you can get the .xsa file that include the .hwh file

[@emiliomartineziii2980]

@@陳立勝-z3iI included that file and it still did not work

[@thanatosor]

Make the algorithm in HLS/C then add to Vivado as IP Design, finish the block then export/generate BitStream to be called in Overlay.

[@Ribbles22]

Why did vivado add the AXI interconnect? Is that because adder.cpp pragma is set to use INTERFACE s_axilite?

[@abuali5513]

Greater video. Thank you

[@emiliomartineziii2980]

This tutorial no longer seems to work in 2024. Does anyone know why?

[@kevingonzalez2927]

it works in vivado 2019.1 for me, where I use Pynq Z2 on its v2.5 image

[@emiliomartineziii2980]

@@kevingonzalez2927I got it to work but I had to use slightly different steps

[@grantolson]

I got it to work on Vivado 2024.2. The biggest thing is that "Vivado HLS" in the video is now a tool called "Vitis" . Some of the options and screens are different, but I was able to pause at each thing he selected in the video and figure out what the new option was. Then later on for Pynq 3.0 I needed to copy the generated .hwh file instead of the .tcl file so that Pynq could load the bitstream. Hope that helps, it's been extremely frustrating to me that 2402.2 is different enough that I can't just follow along with pretty much all the existing tutorials.

[@MichalMonday]

That's very useful, thanks.

[@swery11]

Is it the same if I use this as it is in vitis?