When VDs is increased beyond Vp, the depletion region or layers expand at the top of the channel. The channel now acts as a current limiter and holds drain current constant at Idss. The region between Vp and VDs (max) is called as active region & for proper function VDs is kept between this two levels otherwise is VDs is increased beyond VDs (max) breakdown occurs in JFET .
**** 100% CORRECT ANSWER **** When we increase Vds further after Vp , the drain current (Id) will remain constant( i.e Idss ) for some time but at a voltage Vds=Vds max (Vds max > Vp), the drain current increases enormously almost independent of the applied voltage Vds.This condition is called breakdown of JFET.(Similar to breakdown in output characteristics of BJT)
Just support me if I am correct.... is it becoz of the reason the applied Vgs(>0) has to first break the internal voltage of jfet (till then Idss is 0) & then Id current shoots up as width of d- layer decreases?
But on increasing further more voltage ,than Vp, two depl. Region would touch and current flow would stop thereby rev. Biased pot will be gone. As soon as depl. Region becomes to its natural width, again curr. try to flow, which in turn cause increased depl. Region. Thus we can conclude that curr will not increase further, more than Idss, neither break down point will b acheved ever.
Thanks you so much sir. You are saving lives. I have been recommending your videos to my friends especially electrical engineering students who are taking Analog electronics. Keep producing quality!
When Vds=Vp, depletion region touch each other and Id=0 but this is not possible but as per your graph when Vds>Vp Id remains constant and the depletion region's width will not increase more
Reading from boylestad…. If VDS is increased to a level where it appears that the two depletion reasons would touch the condition referred to as pinch off will result. the level of VDS that establishes this condition is referred to as a pinch off voltage and denoted by VP. in actuality the term pinch of is a misnomer in that is suggest that the current IDis pinched off and drops to 0A . however this is hardly the case ID maintains a saturation level defined as IDSS in reality a very small channel still exist with a current of very high density the fact that ID does not drop at Pinch of and maintains The saturation level is verified by the following fact the absence of a drain current would remove the possibility of different potential levels through the nchannel material to establish the varying level of reverse bias along the PN junction. the result would be a loss of the depletion region distribution that causes pinch off in the first place
I realy understand your teaching style. And i want a professor like you. Sir, do upload the complete concept of every topic you starts. If possible please upload the remaining topics of FET module. MESFET AND MOSFET's . Almost everyone have exams in coming 2-3days. Please uplaod the remaing asap! Thank you sir!
The depletion layer will remain constant because at Vds>Vp Ids/Id is constant. Thanks for your easy interpretation . Please, Upload more videos and Keep it continuing .
Increasing Vds beyond Vp lengthens the contact of the two depletion regions along the channel, but Idss remains constant. Under this condition, the JFET acts as a current source. The channel cannot close completely at pinch-off value, reducing Id to zero - instead, Id retains the saturation level
At 7:47... You told that "when drain current becomes zero then potential drop across channel resistance becomes zero.. So the diode will no longer be reverse bias". Now my question is " let us take Vds=4v at which the channel pinch off occurs and from diagram it looks drain current should become 0 at pinch off voltage. Now if drain current becomes 0 then voltage drop across channel resistances will be 0. Till here you are wright. Now you told - both P and N side will be connected to 0 potential..... But how? If drain current becomes zero then the potential drop will be zero. If potential drop will be zero then the potential at the middle of the channel and at each and every point of the channel which will be equal to drain terminal voltage.(Vds=4). So in this case also p side is connected to zero potential and n side is connected to potential of 4 volt. So here also diode is reverse bias. Now.... Sir... you explain me how you told diode will no longer be reverse bias?If you will see my comment then please answer it sir. I have searched everywhere but I am not finding proper answer.
one question: You said that when depletion layer causes resistance to the flow of electrons,right? So, when the Vdd increases and the depletion layer increases to the pich off point, there will obviously be maximum resistance to the electrons right. So won't current decrease? and when Vd is increasing, current is increasing, why? My question is, at pinch off, does the current increase or decrease?
Many people seem to have the same doubt, I think (i'm not an expert) that while increasing Vdd will make the depletion region grow, the decrease of current because of that is not comparable to the increase of current the Vdd itself is creating (because of omh's law). So the higher the Vdd the narrower the path, but more density of electrons there will be (kinda like pinching a hose). Maybe think of it as the narrowing of the path is compensated with an increase of electrons flow in the constant region of the graph. At least that's my theory, i could be very wrong.
When we increase Vds further after Vp , the drain current will remain constant( i.e Idss ) for some time but at a voltage Vds=Vds max , the drain current increases enormously almost independent of the applied voltage Vds.This condition is called breakdown of JFET.(Similar to breakdown in output characteristics of BJT) REPLY
When Vds is greater than Vp the pinch-off occurs. If we further increase Vds i.e. Vds>Vp, now the constant current 'Id' flows from pinched off point to the source terminal ( the n-channel is treated as a variable resistor so has a voltage difference between pinch-off point and source). Thus current flows from pinch-off point to source which is constant for any value of Vds>Vp.
->The voltage at which the channel closes is called the “pinch-off voltage”, ( VP ). When VDS is increased beyond the pinch off voltage, VGS (Gate Voltage) controls the channel current and VDS has little or no effect ie: remains constant. ->Operating with the Drain Source voltage above Pinch Off is known as the "Saturation Region" as the JFET is acting like a saturated transistor; that is any increase in voltage does not produce a relative increase in current
As Vds increases from 0V to Vp, drain cuerrent increases. As Vds reaches the value of Vp, odrain current levels off and remain constant for all values od Vds between Vp and breakdown voltage.
if we increase Vds greater than Vp the current Id remains constant and the depletion layer can't touch each other and be like as it is in pinchoff voltage
As Vds is increased beyond Vp, the region of close encounter between the two depletion regions will increase in length along the channel, but the level of Id remains essentially the same. In essence, therefore, once Vds Vp the JFET has the characteristics of a current source. The current is fixed at ID IDSS, but the voltage VDS (for levels VP) is determined by the applied load.
00:06 Pinch-off voltage is discussed in this presentation. 01:45 The end channel provides resistance to current ID in the circuit. 03:19 The pinch-off voltage is 1.5 volts in the N channel. 04:41 Pinch-off voltage is the voltage at which the two depletion regions of a MOSFET touch each other. 06:00 Pinch-off voltage is the voltage at which the two depletion regions resemble a pinch. 07:18 Pinch-off voltage is the voltage at which the depletion regions of a PN junction in a MOSFET do not touch each other. 08:48 The pinch-off voltage is the voltage at which the drain current becomes constant. 10:26 IDs is the maximum drain current. Crafted by Merlin AI.
Sir, many of us are in need of further videos on signals and systems...I am following analog circuits also..please can u do both of the subjects...It would be very helpfu for my gate 17
Where are you now .. Is neso academy lecture are beneficial for gate ECE like that of kreatryx channel I follow lecture of neso academy for analog , signal & system, network theory
Operating with the Drain Source voltage above Pinch Off is known as the "Saturation Region" as the JFET is acting like a saturated transistor; that is any increase in voltage does not produce a relative increase in current.
Sir , ur already told that when we are increasing the Vds then at some voltage Id=0 then the depletion region cannot increase furtherbut in later in the graph at Vp the Idss =4v . But ur already told that Id=0
current remains constant and depletion length will also remians constant but after some time as we go on increasing the voltage the transistor will burn,even though they are stable for the temperature it might not bear that much temperature,it stops working and after all it burns off
As the Vds is increased beyond the Vp 1)then there will be no increase in the depletion region because the potential at the pinchoff is 0V and it is also 0V at the gate side 2)the Id current become constant and will not increase further
Sir, according to your explanation when two depletion region touches each other then Id=0 and then depletion region wont increase furthermore. So depletion regions gonna touch each other first, r8. Why it's called they will never touch eaxh other.
first of all,the depletion region will never touch each other as because the voltage of the surrounding part of the "almost touching region" will be closer to 0v and the p-n junction of gate to source will no longer be reverse biased. ^-^
(Vds max > Vp) , it happens breakdown point [ diplation layer density decrease and decrease and lastly the layers broke and the n-conduction channel suddenly increased high and (Id) flows max] My question- in breakdown, the JFET is Destroyed?
amazing explanation sir if vdd will be increased more than vp then id will become coantant and will be called as idss (maximum drain current) and the depletion layer will be almost toching each other.
SIR when Vdd increasing depletion lays will increase and Id current will become zero but deplision layes will not decrease direct 2V = Vd will comes in place of 1.5v i.e revrise voltage is still more increasing
When Vds increases beyond Vp the depletion layer also increase but at very slow rate and we assume Id to be constant but when the length of depletion layer become comparable with the length of JFET the Id will increase with Vds .
Why is Id increasing upto Vp? With increase in Vds the depletion region increases thus limiting the current. Then shouldn't it decrease and then saturate?
I dont get it, how come the resistance as VDS gets closer to VP is constant? shouldnt it be increasing? since the channel gets narrower...but if that is the case, shouldnt ID be decreasing till its smol af? why the graph show that ID increases?
@08:01 we are talking about why Id is not becoming 0......but what you are saying that when id=0, it will no longer be reverse biased then again current starts flowing...but that is the question Id never becoming zero instead of this it is constant ...why...if u are seeing this please try to answer
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When VDs is increased beyond Vp, the depletion region or layers expand at the top of the channel. The channel now acts as a current limiter and holds drain current constant at Idss. The region between Vp and VDs (max) is called as active region & for proper function VDs is kept between this two levels otherwise is VDs is increased beyond VDs (max) breakdown occurs in JFET .
what do u mean by breakdown here?...is it damaged?
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Hello sivani
@@rickerbarren8469 hi
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Hi
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**** 100% CORRECT ANSWER ****
When we increase Vds further after Vp , the drain current (Id) will remain constant( i.e Idss ) for some time but at a voltage Vds=Vds max (Vds max > Vp), the drain current increases enormously almost independent of the applied voltage Vds.This condition is called breakdown of JFET.(Similar to breakdown in output characteristics of BJT)
Just support me if I am correct.... is it becoz of the reason the applied Vgs(>0) has to first break the internal voltage of jfet (till then Idss is 0) & then Id current shoots up as width of d- layer decreases?
.
@Supratim Debnath
I didn't understand bro Pls explain once again
But on increasing further more voltage ,than Vp, two depl. Region would touch and current flow would stop thereby rev. Biased pot will be gone.
As soon as depl. Region becomes to its natural width, again curr. try to flow, which in turn cause increased depl. Region.
Thus we can conclude that curr will not increase further, more than Idss, neither break down point will b acheved ever.
Thanks you so much sir. You are saving lives. I have been recommending your videos to my friends especially electrical engineering students who are taking Analog electronics.
Keep producing quality!
If we increase further Id then depletion region is breakdown and Id sudden increase and that region is called cut off region
I have to sat that All your lectures lead me to a point where i can feel that I'm too much interested in Electronic Devices. Thanks Sir.
I am addicted to learn from your videos sir..one after the other I am watching since morning.thank you so much
5:41 Pinch off voltage
8:34 Graph
When Vds=Vp, depletion region touch each other and Id=0 but this is not possible but as per your graph when Vds>Vp Id remains constant and the depletion region's width will not increase more
yupp that is the right answer.
Reading from boylestad…. If VDS is increased to a level where it appears that the two depletion reasons would touch the condition referred to as pinch off will result. the level of VDS that establishes this condition is referred to as a pinch off voltage and denoted by VP. in actuality the term pinch of is a misnomer in that is suggest that the current IDis pinched off and drops to 0A . however this is hardly the case ID maintains a saturation level defined as IDSS in reality a very small channel still exist with a current of very high density the fact that ID does not drop at Pinch of and maintains The saturation level is verified by the following fact the absence of a drain current would remove the possibility of different potential levels through the nchannel material to establish the varying level of reverse bias along the PN junction. the result would be a loss of the depletion region distribution that causes pinch off in the first place
I realy understand your teaching style. And i want a professor like you. Sir, do upload the complete concept of every topic you starts. If possible please upload the remaining topics of FET module. MESFET AND MOSFET's . Almost everyone have exams in coming 2-3days. Please uplaod the remaing asap! Thank you sir!
The depletion layer will remain constant because at Vds>Vp Ids/Id is constant. Thanks for your easy interpretation . Please, Upload more videos and Keep it continuing .
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Nice bro your 💯 times better than my professor thank you bro
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Thank you for a detailed description of JFET
That resistor explanation was awsome bro
It is too much helpful Sir. ..because you teach short but smarter
such an detailed explanation :-) if all of you continue to learn this way then all will become scientist one day ;-)
It was really a doubt clearing video
Increasing Vds beyond Vp lengthens the contact of the two depletion regions along the channel, but Idss remains constant. Under this condition, the JFET acts as a current source. The channel cannot close completely at pinch-off value, reducing Id to zero - instead, Id retains the saturation level
At 7:47... You told that "when drain current becomes zero then potential drop across channel resistance becomes zero.. So the diode will no longer be reverse bias".
Now my question is " let us take Vds=4v at which the channel pinch off occurs and from diagram it looks drain current should become 0 at pinch off voltage. Now if drain current becomes 0 then voltage drop across channel resistances will be 0. Till here you are wright. Now you told - both P and N side will be connected to 0 potential.....
But how?
If drain current becomes zero then the potential drop will be zero. If potential drop will be zero then the potential at the middle of the channel and at each and every point of the channel which will be equal to drain terminal voltage.(Vds=4). So in this case also p side is connected to zero potential and n side is connected to potential of 4 volt. So here also diode is reverse bias.
Now.... Sir... you explain me how you told diode will no longer be reverse bias?If you will see my comment then please answer it sir. I have searched everywhere but I am not finding proper answer.
Si,
please add different types of oscillators videos..
Your videos are easy to learn concept.👍👍
Tanks u..
one question:
You said that when depletion layer causes resistance to the flow of electrons,right? So, when the Vdd increases and the depletion layer increases to the pich off point, there will obviously be maximum resistance to the electrons right. So won't current decrease?
and when Vd is increasing, current is increasing, why?
My question is, at pinch off, does the current increase or decrease?
Current didn't decrease, it becomes constant.
Many people seem to have the same doubt, I think (i'm not an expert) that while increasing Vdd will make the depletion region grow, the decrease of current because of that is not comparable to the increase of current the Vdd itself is creating (because of omh's law). So the higher the Vdd the narrower the path, but more density of electrons there will be (kinda like pinching a hose). Maybe think of it as the narrowing of the path is compensated with an increase of electrons flow in the constant region of the graph. At least that's my theory, i could be very wrong.
@@guidoglielmi7992 I think you're right.
@@guidoglielmi7992 ur theory was good
Respect from Ethiopia.
When we increase Vds further after Vp , the drain current will remain constant( i.e Idss ) for some time but at a voltage Vds=Vds max , the drain current increases enormously almost independent of the applied voltage Vds.This condition is called breakdown of JFET.(Similar to breakdown in output characteristics of BJT)
REPLY
You are an awesome teacher for sure 🙏the topics seem easier watching your videos🙂
really great explanation Sir...very nice and helpful
Nice Explanation . Thank you sir❤
Sir your way of teaching is really excellent
Amazing videos sir,keep up the great work
When Vds is greater than Vp the pinch-off occurs. If we further increase Vds i.e. Vds>Vp, now the constant current 'Id' flows from pinched off point to the source terminal ( the n-channel is treated as a variable resistor so has a voltage difference between pinch-off point and source). Thus current flows from pinch-off point to source which is constant for any value of Vds>Vp.
->The voltage at which the channel closes is called the “pinch-off voltage”, ( VP ). When VDS is increased beyond the pinch off voltage, VGS (Gate Voltage) controls the channel current and VDS has little or no effect ie: remains constant.
->Operating with the Drain Source voltage above Pinch Off is known as the "Saturation Region" as the JFET is acting like a saturated transistor; that is any increase in voltage does not produce a relative increase in current
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As Vds increases from 0V to Vp, drain cuerrent increases. As Vds reaches the value of Vp, odrain current levels off and remain constant for all values od Vds between Vp and breakdown voltage.
When we increase Vgs , junction will be in forward biased hence depletion region becomes negligible due to this Id will increase enormously
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if we increase Vds greater than Vp the current Id remains constant and the depletion layer can't touch each other and be like as it is in pinchoff voltage
Thank you sir,.u r the best
Thank you sir 😊🤟
Thanks Sir,, this is a perfect definition on pinch of voltage... Thanks once again Sir..
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As Vds is increased beyond Vp, the region of close encounter between the two
depletion regions will increase in length along the channel, but the level of Id remains
essentially the same. In essence, therefore, once Vds Vp the JFET has the characteristics of a current source. The current is fixed at ID IDSS,
but the voltage VDS (for levels VP) is determined by the applied load.
Nice explanation 🙏👏
Thank you sir
Your teaching skill is very good
Now my all doubt cleared
please add the concepts of mosfet too.
Thanks for mentioning the time of starting, saved a lot of time
Thank you very helpful
best way of explaining nice channel
depletion region will remain same for vds>vp as it is at vds=|vp|.And id also remains same
i hve my Ae exam on 25. So it wud b great if u upload some more videos on jfet✌
No change id remains constant &there may be increasing of temeperature
good explanation sir
These videos really help.... thank you!
I think after pinch voltage, there's breakdown of deplition layer and Id increases abruptly
Current ID becomes constant after Vp so where does it becoming zero ? pls explain
great explanation
On increasing Vdc > Vp until Vds max Current Idss remain constant but after Vds max breakdown occurs resulting sharp flow of current.
00:06 Pinch-off voltage is discussed in this presentation.
01:45 The end channel provides resistance to current ID in the circuit.
03:19 The pinch-off voltage is 1.5 volts in the N channel.
04:41 Pinch-off voltage is the voltage at which the two depletion regions of a MOSFET touch each other.
06:00 Pinch-off voltage is the voltage at which the two depletion regions resemble a pinch.
07:18 Pinch-off voltage is the voltage at which the depletion regions of a PN junction in a MOSFET do not touch each other.
08:48 The pinch-off voltage is the voltage at which the drain current becomes constant.
10:26 IDs is the maximum drain current.
Crafted by Merlin AI.
Sir, many of us are in need of further videos on signals and systems...I am following analog circuits also..please can u do both of the subjects...It would be very helpfu for my gate 17
Where are you now ..
Is neso academy lecture are beneficial for gate ECE like that of kreatryx channel
I follow lecture of neso academy for analog , signal & system, network theory
Hello how are you?
Operating with the Drain Source voltage above Pinch Off is known as the "Saturation Region" as the JFET is acting like a saturated transistor; that is any increase in voltage does not produce a relative increase in current.
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great work sir.....plz upload more video of fet
Excellent sir..
very good video ...in easy way we understand. ...examples are good ..it is easy to understand. ..
Sir please post problem solving videos sir
On increasing of Vds beyond Vp the breakdown occurs called as avalanche breakdown
Sir u r god's gift for us sir.Thank u so much sir . Thank to.
Sir , ur already told that when we are increasing the Vds then at some voltage Id=0 then the depletion region cannot increase furtherbut in later in the graph at Vp the Idss =4v . But ur already told that Id=0
yeah what is going on ? anyone has the answer?
But it was not id =0,the minimum current flow will maintain that called IDSS then we can assume id =0=idss 👍
current remains constant and depletion length will also remians constant but after some time as we go on increasing the voltage the transistor will burn,even though they are stable for the temperature it might not bear that much temperature,it stops working and after all it burns off
What is the reason for writing the pinch off voltage in a negative value. Please explain
Vp will be negative for n-channel JFET
Ur the best teacher I have ever seen
As the Vds is increased beyond the Vp 1)then there will be no increase in the depletion region because the potential at the pinchoff is 0V and it is also 0V at the gate side
2)the Id current become constant and will not increase further
Sir, according to your explanation when two depletion region touches each other then Id=0 and then depletion region wont increase furthermore.
So depletion regions gonna touch each other first, r8. Why it's called they will never touch eaxh other.
first of all,the depletion region will never touch each other as because the voltage of the surrounding part of the "almost touching region" will be closer to 0v and the p-n junction of gate to source will no longer be reverse biased. ^-^
Drain current becomes constant when we increase drain voltage greater than pinchoff voltage as it is clear from graph also
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This is really helpful thank you sir......
Anjali Jaswal yes
(Vds max > Vp) , it happens breakdown point [ diplation layer density decrease and decrease and lastly the layers broke and the n-conduction channel suddenly increased high and (Id) flows max]
My question- in breakdown, the JFET is Destroyed?
amazing explanation sir
if vdd will be increased more than vp then id will become coantant and will be called as idss (maximum drain current) and the depletion layer will be almost toching each other.
Thanks a lot.
SIR when Vdd increasing depletion lays will increase and Id current will become zero
but deplision layes will not decrease direct 2V = Vd will comes in place of 1.5v i.e revrise voltage is still more increasing
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When Vds increases beyond Vp the depletion layer also increase but at very slow rate and we assume Id to be constant but when the length of depletion layer become comparable with the length of JFET the Id will increase with Vds .
Well Explained , Thank you, Sir :).
Sir u already told that at pinch off voltage Id =0 then in the later graph at VP how id becomes max..?
Sir ji bahut badhiya
Why is Id increasing upto Vp? With increase in Vds the depletion region increases thus limiting the current. Then shouldn't it decrease and then saturate?
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I dont get it, how come the resistance as VDS gets closer to VP is constant? shouldnt it be increasing? since the channel gets narrower...but if that is the case, shouldnt ID be decreasing till its smol af? why the graph show that ID increases?
Best concept at 8:00
Why we take n channel as a four resistance
sir please explain the topic i.e, transistor as an amplifier
@08:01 we are talking about why Id is not becoming 0......but what you are saying that when id=0, it will no longer be reverse biased then again current starts flowing...but that is the question Id never becoming zero instead of this it is constant ...why...if u are seeing this please try to answer
Home work -depletion region uniform and current will remain maximum
Vd is at max level only it is always be VD greater than VP so ,there is no change in depletion region and Id.....
wrong
vds increase by one vpo, id remains costance at is maximum valu certain idss upto certain point . in due to fact that Rds increase.
don't you think the transition should be smooth in current characteristic Id vs vDS?