- Видео 34
- Просмотров 23 254
VLSI Gyan
Индия
Добавлен 28 янв 2021
VLSI Gyan: Unleashing the World of VLSI Design and Beyond
Hi welcome to my channel.
My channel is dedicated to providing you with in-depth knowledge, insights, and practical tips to excel in the field of Very Large Scale Integration (VLSI).
Please Join me for exploring latest advancementsand industry trends in VLSI design and variety of topics, including digital and analog circuit design, system-on-chip (SoC) integration, ASIC and FPGA design methodologies, verification techniques.
From fundamental concepts to advanced techniques that caters to both beginners and professionals.
Subscribe to my channel and hit the notification bell to join a community of VLSI enthusiasts, engineers, and students.
#vlsi
#verilog
#rtl
#vlsiprojects
#vlsidesign
#vhdl
#ece
#digitalelectronics
#fpga
#apb
#digitalelectronicslectures
#btech
#btechprojects
#mtechprojects
#mtech
#numbersystem
#memory
#computerorganization
#interview
#placement
#programming
#verilog
#hardwaredesign
Hi welcome to my channel.
My channel is dedicated to providing you with in-depth knowledge, insights, and practical tips to excel in the field of Very Large Scale Integration (VLSI).
Please Join me for exploring latest advancementsand industry trends in VLSI design and variety of topics, including digital and analog circuit design, system-on-chip (SoC) integration, ASIC and FPGA design methodologies, verification techniques.
From fundamental concepts to advanced techniques that caters to both beginners and professionals.
Subscribe to my channel and hit the notification bell to join a community of VLSI enthusiasts, engineers, and students.
#vlsi
#verilog
#rtl
#vlsiprojects
#vlsidesign
#vhdl
#ece
#digitalelectronics
#fpga
#apb
#digitalelectronicslectures
#btech
#btechprojects
#mtechprojects
#mtech
#numbersystem
#memory
#computerorganization
#interview
#placement
#programming
#verilog
#hardwaredesign
The I2C Protocol
In this video i have explained about I2C (Inter- Integrated Circuit)protocol.How the communication takes place in I2c protocol.It is a serial synchronouus protocol.
#rtl
#asics
#digitaldesign
#vlsi
#verilogtutorial
#verilogprogramming
#semiconductor
#vlsidesign
#linting
#cdc
#viralvideo
#viral
#engineering
#mtechprojects
#btech
# Rtl design
#RTL lint
#verilog
# VLSI
#vhdl
#VLSI GYAN
#static timing analysis
#synthesizer
#spyglass
#cadencedesignsystems
#education
#rtl
#asics
#digitaldesign
#vlsi
#verilogtutorial
#verilogprogramming
#semiconductor
#vlsidesign
#linting
#cdc
#viralvideo
#viral
#engineering
#mtechprojects
#btech
# Rtl design
#RTL lint
#verilog
# VLSI
#vhdl
#VLSI GYAN
#static timing analysis
#synthesizer
#spyglass
#cadencedesignsystems
#education
Просмотров: 128
Видео
FPGA vs ASIC
Просмотров 1667 месяцев назад
FPGAs (Field-Programmable Gate Arrays) and ASICs (Application-Specific Integrated Circuits) are both types of integrated circuits used in digital design, but they differ significantly in terms of their architecture, design flow, flexibility, and application scenarios. FPGAs are reconfigurable semiconductor devices consisting of an array of configurable logic blocks (CLBs), interconnects, and I/...
System on Chip (SOC)
Просмотров 2078 месяцев назад
This video is about the SOC ie System on chip ICs .In this video I have discussed about the key aspects,importance,challenges in designing SOC. #rtl #vlsi #verilogtutorial #verilogprogramming #semiconductor #vlsidesign #linting # Rtl design #RTL lint #verilog # VLSI #vhdl #VLSI GYAN #static timing analysis #synthesizer #spyglass #xilinx #vivado #electronic #vlsiprojects #vlsi #ece # design veri...
fpga design flow
Просмотров 5238 месяцев назад
This video explains about the FPGA design process.The different stages involved in FPGA Design process. #rtl #vlsi #verilogtutorial #fpga #verilogprogramming #semiconductor #vlsidesign #linting # Rtl design #RTL lint #verilog # VLSI #vhdl #VLSI GYAN #static timing analysis #synthesizer #spyglass #xilinx #vivado #electronic #vlsiprojects #vlsi #ece # design verification
Common design mistakes: READ WRITE RACE IN VERILOG
Просмотров 1909 месяцев назад
In this video I have explained about read write race in Verilog.Cominational and sequential read write race .Also I have explained about ho to overcome the read write race condition. #rtl #vlsi #verilogtutorial #verilogprogramming #semiconductor #vlsidesign #linting # Rtl design #RTL lint #verilog # VLSI #vhdl #VLSI GYAN #static timing analysis #synthesizer #spyglass #xilinx #vivado #electronic...
APB PROTOCOL
Просмотров 5519 месяцев назад
This video is about the APB protocol.The APB protocol is a low bandwidth,low peripheral protocol used in system on chip designs.It belongs to AMBA protocol family. #amba protocol #systemonchip #embedded_systems #rtl #vlsi #verilog #verilogtutorial #semiconductor #vlsigyan #electronic #ُembeddedsystem #vlsiprojects #vlsidesign #vhdl #ece #fpga #vivado #xilinx #flipflops #digitalelectronics #digi...
The Multi cycle Path in VLSI
Просмотров 1,2 тыс.10 месяцев назад
In this video I have eplained about the multi cycle path.A multi-cycle path is a timing path in a digital design where the data takes more than one clock cycle to propagate from the source (usually a register or flip-flop) to the destination (another register or flip-flop). Multi-cycle paths are often used to optimize critical timing paths in a design where meeting setup and hold time requireme...
Concept of False Path
Просмотров 70711 месяцев назад
In this video I have explained the false path in vlsi."A 'false path' is a path through a digital circuit that is intentionally excluded from the timing analysis. It's a path where the designer knows that signals will not violate the specified clock-to-q delay, and as a result, this path is ignored during the timing analysis process." #timingconstraints #falsepath #rtl #vlsi #verilog #verilogtu...
Clock Skew and Jitter
Просмотров 1,7 тыс.11 месяцев назад
Welcome to our informative video where we demystify two common challenges in the world of digital electronics: Clock Skew and Jitter. Whether you're a student, engineer, or tech enthusiast, understanding these concepts is essential for ensuring the reliable operation of your electronic circuits. Video on CLOCK SKEW ruclips.net/video/6m_oaHL_S08/видео.html #rtl #vlsi #verilog #ُembeddedsystem #v...
Parity Generator
Просмотров 8211 месяцев назад
In this video, we'll delve into the fascinating world of digital logic and we will see how to design and implement a Parity Generator circuit. Whether you're a student, hobbyist, or tech enthusiast, understanding the concept of parity is essential in the realm of data transmission and error detection. #rtl #vlsi #verilogtutorial #verilogprogramming #semiconductor #vlsidesign #parity #errordetec...
FIFO DEPTH CALCULATIONS
Просмотров 2 тыс.Год назад
In this video I have explained the easiest method to calculate the depth of the FIFO.I have taken into the consideration the different scenarios.This video gives the indepth knowledge about the FIFO depth calculations. An introduction to FIFO ruclips.net/video/K5JYQTDMWMw/видео.html #fifo #fifo_depth_calculation #vlsi #vlsidesign #vlsi gyan #verilog #verilogtutorial #fpga #ece #vhdl #semiconduc...
An Introduction to FIFO
Просмотров 772Год назад
In VLSI (Very Large Scale Integration) design and digital circuits, FIFO stands for "First-In, First-Out," which is a type of data storage element used to manage the flow of data between two asynchronous digital circuits. A FIFO is a common building block in digital systems, especially in scenarios where data is produced and consumed at different rates or in different clock domains. The main pu...
Clock Generation Code Using Verilog | Comprehensive Tutorial
Просмотров 483Год назад
Welcome to my Channel VLSI Gyan .In this video Ihave expalined the fundamental concepts of clock generation and demonstrate how to implement a clock generator using Verilog. A clock signal is a crucial component in digital systems, providing synchronization and regulating the timing of various operations. Understanding how to generate an accurate and reliable clock signal is essential for desig...
Lint in RTL Design || RTL Linting || Linters
Просмотров 5 тыс.Год назад
This video provides a comprehensive introduction to linting, a powerful technique for improving code quality and developer productivity. Linting is a static code analysis process that checks code for potential issues, errors, and violations. It is applicable to various programming languages and domains, with a focus on providing reliable, maintainable, and efficient code. The video begins by ex...
Function and Task in Verilog.Difference between the Function and Task
Просмотров 309Год назад
In this video, I have discussed the concepts of function and task, two crucial constructs that enhance the modularity and reusability of your Verilog code. Whether you're a beginner or an experienced Verilog developer, understanding how to effectively use functions and tasks can greatly improve your design efficiency and code organization. Functions are self-contained blocks of code that take i...
Implementation of Logic Gates using MUX
Просмотров 130Год назад
Implementation of Logic Gates using MUX
Mastering Timing Closure in VLSI: Unleashing Design PerformanceTiming Closure in VLSI TimingAnalysis
Просмотров 1,1 тыс.Год назад
Mastering Timing Closure in VLSI: Unleashing Design PerformanceTiming Closure in VLSI TimingAnalysis
Clock Skew in VLSI.Impact of Clock Skew.
Просмотров 502Год назад
Clock Skew in VLSI.Impact of Clock Skew.
Most Frequently asked Interview questions for RTL Design Engineer
Просмотров 1,8 тыс.Год назад
Most Frequently asked Interview questions for RTL Design Engineer
Hold Time in VLSI. How to fix hold time violation.
Просмотров 190Год назад
Hold Time in VLSI. How to fix hold time violation.
Setup Time in VLSI.. Setup and hold time of flipflops explained . how to fix setup violations..
Просмотров 335Год назад
Setup Time in VLSI.. Setup and hold time of flipflops explained . how to fix setup violations..
SRAM (Static Random Access Memory)with verilog code.Difference between SRAM and DRAM types of RAM
Просмотров 1,4 тыс.Год назад
SRAM (Static Random Access Memory)with verilog code.Difference between SRAM and DRAM types of RAM
Quartus Prime tutorial for beginners.. how to use Quartus prime lite edition..
Просмотров 1,1 тыс.Год назад
Quartus Prime tutorial for beginners.. how to use Quartus prime lite edition..
How to use ModelSim from Scratch for simulating a verilog code for Half Adder
Просмотров 82Год назад
How to use ModelSim from Scratch for simulating a verilog code for Half Adder
SERIAL IN SERIAL OUT Shift Register Verilog code using Xilinx Vivado tool
Просмотров 582Год назад
SERIAL IN SERIAL OUT Shift Register Verilog code using Xilinx Vivado tool
D Flip Flop."Demystifying the D Flip-Flop: Unleashing the Power of Digital Circuits"
Просмотров 175Год назад
D Flip Flop."Demystifying the D Flip-Flop: Unleashing the Power of Digital Circuits"
Really helpful content not avaliable much please keep going
@@kareematef7347 thanks
During simulation i am getting error of invalid licence environment,, what should i do
Have you set path environment variable to C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem? Set PATH=C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem and launch modelsim from tools->run simulation tools->rtl simulation that will launch the modelsim. After this step restart Quartus or system itself. Thankyou
Mam please explain CDC, upf
You are the best instructor on this. Thanks for all the detailed scenarios and great explanation. It was worth my time!
Thankyou
well mam
Please explain the 2ff sychronizer, mux synchronizer, fifo synchronizer, pulse synchroniser, Handshaking mechanism please do one video of this things thanks
Nice explanation thanks
Nice explanation..thank you mam
Nice explanation
Very clear explanation...
Nice explanation
Nice explanation
Mam make a video on spyglass cdc tool
Nice explanation mam
HOW we do linting in real code and how we download tools for that . I think this should be there
Make more videos mam RDC, CDC
Sure
Usually we don’t use = in always @( posedge clk), you can change it into combinatorial logic with always @(*), then you can use =
Can u explain about synchronizers techniques
Great explanation
Thank you
hi, if you don't mind could please do one video on the CDC topic and how to use it in a real-time project with a small example.
What will happen in this case assign a=b assign c=a
Hi Mam, Thanks for this useful content, My request is please provide us the information how to debug in real time or solution or fix for the errors
Great content, 👍
Plz change ppt color... remaining all r good
Thank you for your suggestions..
Mam Why write operation is clock based and rd operation is combinational ? Is that mandatory to be like that. one more doubt was how could we can decide the code is sram by looking code itself.
Sure
Useful for preparing interviews in short period. Thankyou mam
Very clear explanation...
Nice explanation, short and simple useful videos . Thanks mam
Thank you
Ppt color and design , presentation is good !
Very nice explanation Keep going on ✨
Thanks a lot ..
Thanks
How to generate a clock with 1Mhz freq.
We can generate the 1MHz clock by using a counter inside the always block .The counter is used to divide the input frequency to the required frequency. Based on input frequency and output frequency we can select the counter.
Good mam keep it up
Thanks
Be practical about the questions instead of being theoretical. in the 3rd scenario, depth that is mentioned is 1, which is not sufficient, because of write and read pointer synchronization stage (2 Flop up and down)in the asynchronous FIFO, so we need minimum of 5-6 cycles to avoid backpressure which results the depth to be minimum of 6, otherwise FIFO full would be asserted after the 1st write itself.
bhai can u tell from where can we learn fifo ??
well explained 💯
@sadiyakarigar785 Thankyou
Are you have sta material
👇 *PromoSM*
Please upload the videos regularly... Your explanation good 😊
Very good explanation
Nice Explanation..