If I understood this correctly, AEC-101 grade 1 (125C ambient) is equivalent to Synopsys's grade 2 (125C Tjmax),and AECQ101 grade 0 (150C ambient), is equivalent to Synopsys's grade 1 (150C Tjmax)., so is there an assumption that Tj is always +25C over ambient? That plays into a Tjmax of 175C for Synopsys grade 0, but that's when the wheels fall off the bus in terms of packaging failure mechanisms, as CPI starts to take over and wirebonds start failing. and flip-chip delamination and ILD damage begin predominating, correct?
Hi Andy, the issue here is created by the fact that the AEC-Q100 specifications use ambient temperatures and there is no such application to semiconductor IP such as a DDR interface. So we translate the AEC-Q100 ambient temperature specifications into equivalent junction temperatures for the purposes of designing and verifying IP. For that purpose, we specify 125C junction for Grade 2 and 150C junction for Grade 1. For a DDR interface, the SoC is typically in the review mirror area or in the console area and Grade 0 is rarely, if ever, required. Grade 0 is usually used under the hood for MCUs and TCUs. Such an environment is also too harsh for the actual DRAMs (high temperature increases the DRAM storage cell leakage through the access transistor resulting in data that can no longer be sensed during a read). And just to keep things interesting, the DRAMs use a different method for specifying temperature, they use Tcase. Check out Micron's excellent technical note on that in "TN-00-08: Thermal Applications". Cheers, ...Graham
@@grahamallan9440 Many thanks: sorry I mis-stated the Q100. As an IP designer, the reliability of the final device must be considered s part of the system, and so include many factors out of your control.
That was great! I like the way he explained the benefits and the differences in needs for all areas. DDR memory is not "VHS" video tapes just yet. I recently purchased a Vega 64 reference model I am pleased with the choice of HBM2 memory. I have mine locked @165W low power setting and I get the increase in performance I was looking for vs. my rx 480 o.c.. I have overtime changed my home office setup to mostly low power or high efficiency electronics. Discussions like this give me ideas of what to look for in future low power high performance designs. My question is can we get a cpu with hbm as a L3 cache or L4? Is that out of the question?
These videos are great - thank you for producing this content!
Nice explanation! clears doubts about all kinds of DRAM's 👏
this really makes sense. thanks for the concise information. I worked with HBM on stratix 10
If I understood this correctly, AEC-101 grade 1 (125C ambient) is equivalent to Synopsys's grade 2 (125C Tjmax),and AECQ101 grade 0 (150C ambient), is equivalent to Synopsys's grade 1 (150C Tjmax)., so is there an assumption that Tj is always +25C over ambient? That plays into a Tjmax of 175C for Synopsys grade 0, but that's when the wheels fall off the bus in terms of packaging failure mechanisms, as CPI starts to take over and wirebonds start failing. and flip-chip delamination and ILD damage begin predominating, correct?
Hi Andy, the issue here is created by the fact that the AEC-Q100 specifications use ambient temperatures and there is no such application to semiconductor IP such as a DDR interface. So we translate the AEC-Q100 ambient temperature specifications into equivalent junction temperatures for the purposes of designing and verifying IP. For that purpose, we specify 125C junction for Grade 2 and 150C junction for Grade 1. For a DDR interface, the SoC is typically in the review mirror area or in the console area and Grade 0 is rarely, if ever, required. Grade 0 is usually used under the hood for MCUs and TCUs. Such an environment is also too harsh for the actual DRAMs (high temperature increases the DRAM storage cell leakage through the access transistor resulting in data that can no longer be sensed during a read). And just to keep things interesting, the DRAMs use a different method for specifying temperature, they use Tcase. Check out Micron's excellent technical note on that in "TN-00-08: Thermal Applications". Cheers, ...Graham
@@grahamallan9440 Much appreciated, sir!
@@grahamallan9440 Many thanks: sorry I mis-stated the Q100. As an IP designer, the reliability of the final device must be considered s part of the system, and so include many factors out of your control.
That was great! I like the way he explained the benefits and the differences in needs for all areas. DDR memory is not "VHS" video tapes just yet. I recently purchased a Vega 64 reference model I am pleased with the choice of HBM2 memory. I have mine locked @165W low power setting and I get the increase in performance I was looking for vs. my rx 480 o.c.. I have overtime changed my home office setup to mostly low power or high efficiency electronics. Discussions like this give me ideas of what to look for in future low power high performance designs. My question is can we get a cpu with hbm as a L3 cache or L4? Is that out of the question?
I think that is what the Fujitsu A64FX does! It has 32GB of HBM2 connected to it's 52 cores!
Answer a little late but the 🍏 M1 chipset utilizes your idea