@Anastasi In Tech - What about using i-squared-l logic and/or vacuum channel FETs, possibly on chiplets? I2L seemed very promising when first introduced, but it's power consumption was high since transistors were all large at that time. As a bipolar technology it will not suffer from gate leakage problems. Are there any other reasons why it might not work? As for "vacuum" channel FETs, they are 10 times faster or more, partly because they use free electrons. They also benefit from nanoscale features, are extremely radiation resistant, and they can operate comfortably at temperatures up to hundreds of degrees Celsius. Also they don't actually require vacuum when built at small nanoscales.
@@fluiditynz - I left my comments and questioon here because it is the most likely place for her to see it. Nothing to do with the laptop she's promoting.
When I first started programming, and RAM was off chip and typically a few KB, we'd spend a lot of dev time working out how to do as much as possible in as little RAM as possible and as few clock cycles as possible. These days the demands to cut development time and get new features out, more driven by senior management and Product Owners than by real customer demand, seems to have ditched those ideas. If it's too slow the customer is expected to just buy a higher spec machine and new developers are taught ways to shorten development time but not execution time. I think that this is a false economy. About 10 years ago I was able to shorten a big data-processing job from 3 days to under 20 minutes, on the same hardware, by applying the techniques I'd learned back in the 1980s to key functions. It took me 5 days, but when this is something that has to be run every week the saving soon stacks up
You are absolutely right. Once I participated in a service job to get a power station running. The problem was to bring the gas engines up and running as fast as possible. After a few days the programmer had been flown in and looked for alternative assembler commands to save a clock cycle here and a clock cycle there.😁
Wirth's Corollary to Moore's Law: Any improvement in Hardware performance will be negated by code bloat at an equivalent rate. Kinda like traffic in London.
It's not a false economy, just a different emphasize due to the change in price structure. In the old days, memory were expensive, so we tried to economize its use. Today's memory are so cheap, that software developing time has become the most expensive part of a system.
@@gorilladisco9108 the cost of memory is largely immaterial. It’s the cost of execution time. Say you’ve got a transaction that currently takes 10 minutes to complete but if the code was optimised would take 7 minutes. To optimise the code would take the developer an extra 5 days effort and the developer earns £30 an hour (that’s the mid-point for a developer where I work), so that’s about £1100 wage cost but once it’s done that cost is done. Once rolled out the application is used by 200 people paid £16 an hour (I have some specific applications we use in mind here). Saving 3 minutes per transaction means either those same staff can process 30% more transactions or we can lose 60 staff at a saving of just over £7000 a day. That extra development time would repay in a little over an hour on the first day and after that would be pure cost saving.
You really have a knack for making complex topics engaging and easy to follow for everyone! Breaking down the challenges of SRAM and introducing phase change memory in such a clear manner is no small feat. Excited for more content like this!
@@nicholasfigueiredo3171 Given the way she talks, I would had guessed her field was steering investors into various markets. The technical run down is useful, but the whole discussion is still clearly framed like "guess whats going to make a lot of money in the near future?".
She is a technology communicator. Learn what science is, please. I'm guessing you are a Republican, so I wouldn't expect you to understand the difference.
The problem with chiplet design is heat management. Since every layer is active, it burns energy and produces heat, and this isn't good. A secondary problem is the bus interconnect because stacking requires shared lanes, so memory layers are in parallel, making the bus interconnect a bottleneck. Last but not least is signal strength and propagation time: stacking layers requires precise alignment and add electron jumping around, so there's a potential limiting factor in electron propagation, noise and eventual errors. This isn't much of a problem if the system is built around it, but it still is a limiting factor. There are solutions: since there's one master and multiple slaves there's no risk of collisions and so you can make a lot of assumptions on the drawing board... but busses are going to become wider and more complex, and that will add latency where you don't want it. My 2 cents.
- I wonder if they run veins of metal in between the layers to send the heat to radiator. - They put L3 cache on the second layer, which by virtue is quite removed from the logic circuits.
I'd be curious about the thermodynamic side effects of phase change memory during transitions as the crystallisation would release heat while amorphization would be cooling
The point "good endurance 2*10^8 cycles" prohibits its use for cache memory. But it's really a viable and competitive option as a replacement for Flash memory!
Thanks. Amazing video. It's kind of interesting how it always comes down to the same principles. First shrinking the size in 2D, then layering stuff, and eventually going into the 3rd dimension. And when that reaches its limits, then change the packaging and invent some hybrid setup. Next, change the materials and go nano or use light etc. instead. Even the success criteria are usually similar: energy consumption, speed or latency, size and area, cost of production, reliability and defect rate, and the integration with the existing ecosystem.
My fave memory joke: Stand in the nutritional supplement section of a store and look at the products with a confused expression. When someone else is nearby, ask "Do you remember the name of that one that's supposed to help memory?"
I worked on micron/intels PCM, optane, for a few years. While we were making peogress on some of the problems you mentioned, the venture ultimately failed due to the economics of producing the chips as well as a lack of customers. Would be cool to see it make a comeback in the future
I thank you for your service. When intel announced that they were ending optane, I bought 6 of those PCIE drives; I caught a fire sale. Those drives are the fastest drives I have for doing some disk intensive Studio work. I wish they could've gotten the price down around $100-$200 dollars for the good stuff. I actually got 6 optanes for $45 a piece. I lucked up and bought a box.
Nice idea. Very similar to Nantero NRAM that also uses Van der Walls effect to provide resistive cells using carbon nanotubes for SSD/DRAM universal memory. I've been waiting for NRAM for 20 years, and it is only now beginning to make it's way into the data centre. Let's hope that this technology takes less time to mature.
It has been discussed for decades that close stacking of chips has advantages of speed and size. The issue is heat generation, thus trying to reduce the total charge (electron count per bit). New memory technology is required with far smaller charge transfered per operation.
The words "dynamic" and "static" are a reference to the powering method between state changes. You kind of hinted at this with the TTL logic diagram, but didn't expand. Static is faster because it doesn't have to wait for the re-fresh cycles before it can change state. Static also runs hotter and consumes more power- there are no free lunches ;-)
Not exactly. DRAM consumes power all the time, because it needs constant refresh to preserve contents. SRAM only consumes power during state change. Both consume some leakage current though, and with that, SRAM consumes more due to having more transistors per bit cell. DRAM also consumes considerable current to change state, because of its larger gate capacitance. Overall, DRAM tends to consume more power per bit but costs less and is more compact, which is why we use it for main memory and reserve SRAM for cache and internal registers.
Very interesting. Thanks for sharing your expertise. There is always something interesting in your videos. At least in the three or four i have seen so far.😊
This sort of tech is very interesting, because depending on how it advances, it stands to change the computing landscape in one or more different ways. If Phase-Change Memory is fast enough and gets good enough density, it can replace SRAM in L3 cache. If the speed cannot get high enough, it could still find use as an L4 cache or a replacement for DRAM. If all else fails, I bet it could give Flash storage a run for its money.
I used to use magnetic memory... when I worked on DEC PDP-8e. It was called core memory, you could actually see the core magnets and wires that were wrapped around the cores.
PCM memory chip technology has been in R&D since the mid 2000s. Intel, StMicroelectronics and Ovonyx were in the game together in a joint development starting around 2005. Samsung was also doing research in PCM. I believe the biggest player now in Micron Technology.. And you are correct about all the advantages of PCM. I believe the two big challenges are being able program the device.into two or more distinct, well defined resistance states reliably coupled with manufacturing very small structures with precise dimensions. Nvidea is talking about PCM.
the NVMe slotted in the DDR5 slot - direct access storage - skipping a part of memory all over.. the system boots from storage/memory - slot 2,3,4 are real RAM just a dime throw
Thank you! Just wanted to say you have a mistake in the figure you show (e.g. 12:38) labelling the latency of flash memory as milliseconds (1/1000s) when, as you say in the audio, the latency is in microseconds (1/1000000s)
Thank you for your presentation. I found it fascinating. The phase change memory, amorphous crystal back to uniform array crystal seems like the mental models used to explain demagnetization around the currie point.
It's quite bizarre that you thought the PCM memory is a future replacement of SRAM, as the it has a switching speed of 40ns (on par with DRAM), according to the paper you cited. This is an order of magnitude slower than SRAM. The current only viable option to replace SRAM is SOT-MRAM, which TSMC is working on. Go research SOT-MRAM😁
It also involves a physical change to the medium, which means wear and limited number of writes. I believe a similar principle has been around since at least the 90s. I used to have a CD-R/W type device that used a laser to heat up spots of a special metallic medium, changing it from smooth to amorphous. Could be rewritten some number of times. I will say though, your point is probably good and valid, but could have been made more constructively.
This is true. PCM is totally useless as SRAM replacement and doesn’t have sufficient speed or rewrite resilience. Honestly, she really failed to understand its use case. It’s a great alternative to floating-gate FLASH memory, not SRAM!
So each of the 2 phases of the PCM has a different resistance, so the computer can tell 1 from 0? Can PCM memory be integrated in the same chip as the processor core? Seems like it requires a unique material to be added on a chip
Loved the graph you put together with the memory pyramid (access time vs where is used, with volatility information)!! P.S. Your accent also becomes more and more easy to understand!
Great stuff. As someone who built their own desktops through computer conventions in the 90s I appreciate you bringing me up to date on where we stand now in personal computer development😊
Thank you for this video. It's great. My two issues: (1) heat dissipation, is not addressed (over cycles there is growth of H.A.Z.), (2) One thing I heard about and remember vaguely, was an attempt at self healing logics (rather, materials + control circuitry), which is aimed at reducing the need for redundancy, in elements at the core of the chip (hottest and fastest environment), and attempts to also better the chip lifetime (cycles 'til dead). -I would be grateful if you could address both.
As always fantastic work. I am not so enthusiastic right now with the new technology an endurance of 2E8 is amazing for something like storage, but the computer will go over that in no time for the cache. Even a microprocessor that is not super scalar and runs on the ghz range will be accessing memory in the other of 10^9 per second. Clearly, that access is per cell, and not for the full memory but they need to improve that number a lot.
Paul Schnitzlein taught me how to design static RAM cells. This video speaks to me. Yes the set/clear, and sense amps are all in balance. It is an analogish type circuit that can burn a lot of power when being read.
Great video - thank you Anastasi :-) I think if we stack much more memory as 3rd level cache chiplets on top of CPUs we may reach the size of gigabyte 3rd level cache. And this would eliminate the external DIMMs on the mainboard which makes future Notebooks and PC again cheaper and reduces not just the complexity of the mainboard but also of the operating system, drivers and firmware because data can be loaded directly via fast PCIe lanes connected SSDs to 3rd level cache.
Stacking silicon...who woulda thought ...now it makes perfect sense for chip real estate. Thank you for your brilliant assessment of the latest chip technology. You have expanded my knowledge regularly.
I remember hearing about the SRAM scalling issue some time before the Zen4 release, but then haven't heard anything even though I kept hearing about shinking nodes. Been curious what was coming of that. I was thinking that since it's not benefiting from the scaling, if it may have been counterproductive regarding degradation etc. I wonder if that is what is happening with the Intel 13 and 14K skus? I guess we will find out soon enough. Thanks for the update, I'm glad they are on top of it!
Thanks for the updates, really informative... I was working on OTP memory designs and this new time of glass memory is looking similar to the concept of OTP memory, may be we can see this kind of evolution in OTP memories side also.
What about keeping the heat down. Sure lower power required in some case but stacking should also increase the requirement for improved cooling perhaps?
Yes, though theres more limitations, it's really hard to manage heat in a 3d structure. It also requires new innovative ways to do it. This is why a room temperature super conductor would be such an amazing breakthrough. You wouldn't need to worry about heat management and you could up the frequency to Thz levels while maintaining manageability even in a 3d transistor structure. Computing would be millions and billions and even trillions of times faster
Non-volatile and low-latency at the same time, coupled with scalability and hopefully cost-effectiveness in manufacturing, would be a huge technological leap. Thank you for the information.
I believe that down the line we would need to use another processor architecture than the Von Neumann one that we use today (i.e. having logic and memory separated), an architecture that instead has an "on memory compute" design, or perhaps a mix of them. In the end the speed of light makes it hard to compute over longer distances (i.e. CM or even MM) specially when the frequency goes up and the data becomes even larger.
Interesting idea, but very speculative and in need of a demonstration at scale to assess its practicality. Moreover, although a 23% decrease in area is good for an existing bottle neck, it is not revolutionary, that would need a factor of at least 10. At the current estimated level of improvement it becomes a commercial decision on whether this improvement has a fast enough pay back to justify the r&d costs to make it practical. Is anyone making the investment to commercialize this discovery? Thank you for sharing!
Not really, the silicon lattice constant is only 0.7 nanometers. We can't scale in silicon below that. Germanium has a lattice constant of about 0.5. While process nodes and technology are mostly marketing terms and there is room for improvement beyond "1 nanometer process" - we are about at the end of what we can achieve with existing semiconductor paradigms. It will be almost all architecture and material sciences by 2030. We can't get much smaller. A 20% improvement over SRAM is disruptive even if it doesn't scale any smaller. SRAM is unable to be scaled any smaller due to the physics underwriting operation. We only have a few more die shrinks left before we are up against the size of the atom. ... Again, sort of ... A 1 nanometer node doesn't necessarily mean that you can make a grid of 1 nanometer square pads separated by 1 nanometer troughs on all sides, or vice-versa. But as I mentioned, the lattice constant of silicon is 0.7 nanometers, their latest process node is 1.4 nanometers. You can't really cleave off half a crystalline arrangement without having weird things happen, the next die shrink, if it is possible, would come at 0.7 nanometers. We would be, assuming we can make the grid arrangement described, making the smallest transistors possible with silicon, using existing paradigms.... And whatever paradigm comes next would need to use atoms much more efficiently - or some other concepts entirely - to function. On the plus side, it means that in about another 10 years, we might see computers built with the idea they could last decades in their application.
@@Aim54Delta Great points! Thank you for expanding on the technological limits of the underlying physics not covered in the video. Given these fundamental limits to silicon, research efforts will move to entirely different concepts that may or may not work. Perhaps we will not see much further progress ending the decades long run of ever increasing chip performance or something new will make current silicon architectures obsolete. Fascinating field with huge commercial risk/rewards for company boards to ponder. Thank you for your comments.
@@Aim54Delta This is not true. While it is true that the Si Lattice constant is 0.7 nm, it is not true that a 1nm process node actually has features that are 1nm big. For instance, the smallest feature on a "3nm" node is around 20nm. There is plenty of room left for atleast 10 years. For instance, see IMEC's roadmap, which targets A2 (0.2nm equivalent) by 2036.
@@SomebodyHere-cm8dj I recognized that in the original post, yet will simply respond with "I do not share their optimism." We've built at that scale, before, and you need to redesign the device in ways that don't really gain you much. Charges at the atomic scale propagate more according to probability and the ends of an electron's wave function become a serious problem. Not only does this lead to leaking transistor gates, it leads to a form of crosstalk as you have electrons smearing their existence all over the places you don't want them. It's similar to the ghz barrier of data busses. A 100mhz bus has a wavelength of around 2 meters, so you have about 1/4 - or 0.5 meters to play with as a mostly standard wire before you have to worry about the properties of transmission lines. By the time you reach 1Ghz, however, a full wavelength is only 22cm, and you have about 5cm before you're working with a transmission line, and that's so short that it ultimately influences every bus. There are other factors as well, stability of clock pulses, less margin for different propagation times on lines, impact of various sources of capacitance or inductance, etc - all of it compounds to make a business operating above 1GHz a completely different class of engineering and design problems not implied by the simplicity of designing a 800Mhz bus for system RAM. Once you redesign the concept of a data bus to be a transmission line, you have a new system to scale, but it requires that paradigm shift of rethinking the wire. Same thing with semiconductor lithography scaling.
One of the chief benefits I can see in going to optical computing is the ability to have associative addressing through polarization and muliple concurrent optical reading/writing heads for raid like processing.
Feel free to correct me, but isn't the problem with memory scaling really more an artifact of process node naming... we haven't really been shrinking gate sizes to the extent the node names suggest for years. New process nodes are more or less just making the gates more efficient, the names are almost arbitrary. Where in the past they were linked to gate size. These improvements do allow for some better density, but mostly its improvements in current leakage. which improves power consumption and thus clock speed. Memory capacity which is nearly 1:1 linked to transistor density is just scaling at the true rate of density improvements.....
If you translate density scaling into Denard scaling which is related to the impedance of a device then what you said is somewhat true. The issue is that impedance is no longer scaling at the same rate as density. So circuits got smaller but impedance is barely moving.
3 nm and so on is a marketing term that has no relation to any dimension of the transistors anymore. The true gate width until now is 14 nm due to asml's lithography machines limitation. The next step for the next decade is going down to 8nm (about 80 atoms wide).
The BCM2837 SoC chip uses stacked RAM. The Raspberry Pi Foundation released the Pi Zero 2W in 2022 using it. So who stacked first? Regardless of who, it’s great to hear the designers are finding solutions to such huge (microscopic) problems!
My concern with the phase change memory is just the lifetime and reliability. Do the cells grow oxides or change chemistry over time? Can they be ruined by ripple or electrical noise at scale that hasn't been discovered yet? Etc. Love your videos!
It should be mentioned that process node sizes like N3 or N5 nodes are density measurements and not actually a transistor size. Intel 10nm was equivalent to TSMC 7nm as they average over different area sizes and utilize different shapes and can't be compared directly or even with the size of a silicon atom which is only 0.1 nm in "size".
I worry about using non-volatile memory for primary or cache memory because of the security aspect. If the information remains after power is interrupted, quite a few "secrets" will be in clear text, and the determined and well equipped "bad actor" will be able to extract surprising amounts of information from a system. My industry has to issue letters of volatility with everything we produce, and for anything with NVM, the sanitization procedure usually involves removing the part with non-volatile storage and destroying it. The only exception is when it can be proven that the hardware is incapable of writing to that NVM from any component present on the assembly, even if malicious or maintenance software is loaded onto the device. This phase change memory built in the same package as the CPU logic could not be provably zeroized without some sort of non-bypassible hold up power, and that would increase the cost and size of the chip package. I think this is very promising for secondary addressable storage, but I don't see it replacing main memory in most applications.
I had thought of building memory (and the whole IC) in 3D 10 years ago. I think I even put the idea in my website years ago. One part of my idea that is not used yet is using microfluidics to cool the chips that are stacking transistors in 3D, thus restricting heat transfer. The channels could run many levels, and of course, they need fluid-tight connections (a big problem). And use optics to communicate instead of a BUS. Possibly LED or laser tech.
I love the way you explain the topic it gets me thinking even though I have no idea. Like possibly folding the memory and interconnecting them to form cubes cause I always see dies represented in 2d. Like I said, not my field.
Thank u for pointing this out!👍Not just on chip SRAM memory, but operating memory in general has a lot of catchup to do with the compute logic not only because of the limitation of further shrinking SRAM and demand from the AI workloads. Operating memory has been historically left behind the compute logic and in a way ignored "nature's" way of things (brain neurons) by being the same and as fast as compute/processing while having sufficient capacity. Maybe PCM or other memory technologies will deliver that in the future, however I agree with u that L1 cache will most definitely continue to use SRAM for the foreseeable future and L2/3/4 with larger capacities will most likely go first with the stacked SRAM before moving to new technology like PCM or resistive memory.
when you get close to the size of an atom, which i think is close to 0.5nm you run into problems that can not be fixed. In particular, your going to run into the problem that highly focused mental intent will interfere with the operation of the chip itself. You also can not shield this - not in a compact way. It all works out in the end because the only reason for continuing to put more and more SRAM on chips is for AI processors. I say it all works out in the end because in roughly 5 years the AI fad will be over with because it will hit both the "human data" barrier (Generative AI needs human data to base it's model off of) and more importantly - the Power Generation bottleneck. There just isn't enough power generation capability for investors to get a ROI in say less than 10 years. A lot of electrical grids are trying to "go green", the problem with that is they're having problems keeping the lights on as it is. With the solar flare activity and the weakening earth magnetic field we will be experiencing about 10 years of very VERY extreme weather. Summers will be hotter, winters will be colder. Meaning? We will need MORE electrical power to keep ourselves cool in the summer and more electrical power to keep ourselves from freezing to death in the winter. Texas had this probably two years ago. The temperature suddenly dipped down so low that the lubricant in the transmissions of the massive wind generators (which power most of their state) FROZE, the wind kept blowing the turbine blades and what happened? The gear boxes exploded, shredding themselves into metallic shrapnel. The only way the Generative AI market can keep going and growing is with Nuclear Power. Problem there is that it takes 10 years to get a reactor online producing power (sometimes longer i'm told from a friend who builds them). Investors are not going to wait around for 10 years to ...probably get their ROI. They'll pull their money out, and all these AI companies that are IPOs are going to go bust. So all of these AI processors are going to be pretty much worthless. Wonder how much gold is in them? hmmmm..
![Noob To Max With DRAGON REWORK In Blox Fruits [FULL MOVIE]](http://i.ytimg.com/vi/LnBMOinoOvA/mqdefault.jpg)
Check out New ASUS Vivobook S 15: asus.click/vbs_anastasi
Please explain why we don't have quantum computers with Ning Li's room temperature superconductor?
@Anastasi In Tech - What about using i-squared-l logic and/or vacuum channel FETs, possibly on chiplets? I2L seemed very promising when first introduced, but it's power consumption was high since transistors were all large at that time. As a bipolar technology it will not suffer from gate leakage problems. Are there any other reasons why it might not work? As for "vacuum" channel FETs, they are 10 times faster or more, partly because they use free electrons. They also benefit from nanoscale features, are extremely radiation resistant, and they can operate comfortably at temperatures up to hundreds of degrees Celsius. Also they don't actually require vacuum when built at small nanoscales.
@@YodaWhat This is about Anastasi's Asus Vivobook commercial she boldly snuck into her main content?
@@fluiditynz - I left my comments and questioon here because it is the most likely place for her to see it. Nothing to do with the laptop she's promoting.
xoxooxoxoxooxox
When I first started programming, and RAM was off chip and typically a few KB, we'd spend a lot of dev time working out how to do as much as possible in as little RAM as possible and as few clock cycles as possible. These days the demands to cut development time and get new features out, more driven by senior management and Product Owners than by real customer demand, seems to have ditched those ideas. If it's too slow the customer is expected to just buy a higher spec machine and new developers are taught ways to shorten development time but not execution time. I think that this is a false economy. About 10 years ago I was able to shorten a big data-processing job from 3 days to under 20 minutes, on the same hardware, by applying the techniques I'd learned back in the 1980s to key functions. It took me 5 days, but when this is something that has to be run every week the saving soon stacks up
You are absolutely right. Once I participated in a service job to get a power station running. The problem was to bring the gas engines up and running as fast as possible. After a few days the programmer had been flown in and looked for alternative assembler commands to save a clock cycle here and a clock cycle there.😁
Wirth's Corollary to Moore's Law:
Any improvement in Hardware performance will be negated by code bloat at an equivalent rate.
Kinda like traffic in London.
It's not a false economy, just a different emphasize due to the change in price structure.
In the old days, memory were expensive, so we tried to economize its use. Today's memory are so cheap, that software developing time has become the most expensive part of a system.
@@gorilladisco9108 the cost of memory is largely immaterial. It’s the cost of execution time. Say you’ve got a transaction that currently takes 10 minutes to complete but if the code was optimised would take 7 minutes. To optimise the code would take the developer an extra 5 days effort and the developer earns £30 an hour (that’s the mid-point for a developer where I work), so that’s about £1100 wage cost but once it’s done that cost is done. Once rolled out the application is used by 200 people paid £16 an hour (I have some specific applications we use in mind here). Saving 3 minutes per transaction means either those same staff can process 30% more transactions or we can lose 60 staff at a saving of just over £7000 a day. That extra development time would repay in a little over an hour on the first day and after that would be pure cost saving.
NO COPILOT! NO RECALL! This future is PRISONPLANET!
You really have a knack for making complex topics engaging and easy to follow for everyone! Breaking down the challenges of SRAM and introducing phase change memory in such a clear manner is no small feat. Excited for more content like this!
👍🏽💚🌴☀️🌏
Has datsbus ended?
@@Panacea_archive 😂😅no..my English is bad🐪☀️
@Magastz love💚and peace 🌏
Not bad on the eyes either
Science communicators who actually are professionals in their field are allways welcome. Thank you Anastasi
I didn't even know she was from the field, I thought she was just smart. But I guess that makes sense
@@nicholasfigueiredo3171 Given the way she talks, I would had guessed her field was steering investors into various markets. The technical run down is useful, but the whole discussion is still clearly framed like "guess whats going to make a lot of money in the near future?".
She is a technology communicator. Learn what science is, please. I'm guessing you are a Republican, so I wouldn't expect you to understand the difference.
The problem with chiplet design is heat management.
Since every layer is active, it burns energy and produces heat, and this isn't good.
A secondary problem is the bus interconnect because stacking requires shared lanes, so memory layers are in parallel, making the bus interconnect a bottleneck.
Last but not least is signal strength and propagation time: stacking layers requires precise alignment and add electron jumping around, so there's a potential limiting factor in electron propagation, noise and eventual errors. This isn't much of a problem if the system is built around it, but it still is a limiting factor.
There are solutions: since there's one master and multiple slaves there's no risk of collisions and so you can make a lot of assumptions on the drawing board... but busses are going to become wider and more complex, and that will add latency where you don't want it.
My 2 cents.
- I wonder if they run veins of metal in between the layers to send the heat to radiator.
- They put L3 cache on the second layer, which by virtue is quite removed from the logic circuits.
Heat, latency, voltage regulation, signal integrity, etc…. Stacked dies has never been simple which is why there aren’t many of them.
I'd be curious about the thermodynamic side effects of phase change memory during transitions as the crystallisation would release heat while amorphization would be cooling
So, the two biggest old school technologies that are slowing progress seems to be memory and batteries.
Yup!
Also, a shortage of railways.
Thanks!
Thank you
The point "good endurance 2*10^8 cycles" prohibits its use for cache memory. But it's really a viable and competitive option as a replacement for Flash memory!
You explain things so well, thanks for a well thought out presentation
Thanks. Amazing video. It's kind of interesting how it always comes down to the same principles. First shrinking the size in 2D, then layering stuff, and eventually going into the 3rd dimension. And when that reaches its limits, then change the packaging and invent some hybrid setup. Next, change the materials and go nano or use light etc. instead. Even the success criteria are usually similar: energy consumption, speed or latency, size and area, cost of production, reliability and defect rate, and the integration with the existing ecosystem.
А потом ещё уйти в 4 измерение:D
And even then after that, when all resources and possibilities are dead, go quantum and use "entanglement" to avoid heat and space limits...
I greatly admire the passion you infuse into your presentations. Your work is outstanding, please continue this excellent effort. Thank you!
Been waiting for your vid.... Love the content
Its interesting that you talk about your experience in chip design. Maybe you cold make a video talking about your experince in chip design?
Subscribed... Always interested in intelligent people. You understand what you are saying and are not just spewing words. Fascinating.
My fave memory joke: Stand in the nutritional supplement section of a store and look at the products with a confused expression. When someone else is nearby, ask "Do you remember the name of that one that's supposed to help memory?"
Thank you Anastasi - great presentation!
I worked on micron/intels PCM, optane, for a few years. While we were making peogress on some of the problems you mentioned, the venture ultimately failed due to the economics of producing the chips as well as a lack of customers. Would be cool to see it make a comeback in the future
I am shocked she failed to mention optane as well - "new technology" lol.
had they holded on till CXL was here imo it could have taken off, it had great promise it was just in the wrong interfaces
I thank you for your service. When intel announced that they were ending optane, I bought 6 of those PCIE drives; I caught a fire sale. Those drives are the fastest drives I have for doing some disk intensive Studio work. I wish they could've gotten the price down around $100-$200 dollars for the good stuff. I actually got 6 optanes for $45 a piece. I lucked up and bought a box.
Nice idea. Very similar to Nantero NRAM that also uses Van der Walls effect to provide resistive cells using carbon nanotubes for SSD/DRAM universal memory.
I've been waiting for NRAM for 20 years, and it is only now beginning to make it's way into the data centre. Let's hope that this technology takes less time to mature.
Very interesting, I like the way you present info clearly and concisely
Amazing!
This girl researched exactly what I wanted to know.
Thanks.
It has been discussed for decades that close stacking of chips has advantages of speed and size. The issue is heat generation, thus trying to reduce the total charge (electron count per bit). New memory technology is required with far smaller charge transfered per operation.
The words "dynamic" and "static" are a reference to the powering method between state changes. You kind of hinted at this with the TTL logic diagram, but didn't expand. Static is faster because it doesn't have to wait for the re-fresh cycles before it can change state. Static also runs hotter and consumes more power- there are no free lunches ;-)
Not exactly. DRAM consumes power all the time, because it needs constant refresh to preserve contents. SRAM only consumes power during state change. Both consume some leakage current though, and with that, SRAM consumes more due to having more transistors per bit cell. DRAM also consumes considerable current to change state, because of its larger gate capacitance. Overall, DRAM tends to consume more power per bit but costs less and is more compact, which is why we use it for main memory and reserve SRAM for cache and internal registers.
Your channel has really improved over the 2 or so years Ive followed you. Im impressed!
Thank you for being here
Very interesting. Thanks for sharing your expertise. There is always something interesting in your videos. At least in the three or four i have seen so far.😊
This sort of tech is very interesting, because depending on how it advances, it stands to change the computing landscape in one or more different ways. If Phase-Change Memory is fast enough and gets good enough density, it can replace SRAM in L3 cache. If the speed cannot get high enough, it could still find use as an L4 cache or a replacement for DRAM. If all else fails, I bet it could give Flash storage a run for its money.
Very comprehensive and interesting video. Thanks Anastasi! 👍
Super great explained in a such complex technology
Well said. Excellent video Anastasi!
Cool video. Perhaps in some future, memory is controlled by shadow? 🤔
😮😮😮 Really liked this info. I'm formative to the point and exciting.
I used to use magnetic memory... when I worked on DEC PDP-8e. It was called core memory, you could actually see the core magnets and wires that were wrapped around the cores.
I love your explanations. Nice work! 👍
Very well explained. Thanks
We need more Journalism with clarity to present for the public the real challenges and advancements of Technology.
PCM memory chip technology has been in R&D since the mid 2000s. Intel, StMicroelectronics and Ovonyx were in the game together in a joint development starting around 2005. Samsung was also doing research in PCM. I believe the biggest player now in Micron Technology.. And you are correct about all the advantages of PCM. I believe the two big challenges are being able program the device.into two or more distinct, well defined resistance states reliably coupled with manufacturing very small structures with precise dimensions. Nvidea is talking about PCM.
That was a great video very informative. You're right, it is an exciting time to be alive with all the evolving technology.
This was an excellent and very informative episode!
the NVMe slotted in the DDR5 slot - direct access storage - skipping a part of memory all over.. the system boots from storage/memory - slot 2,3,4 are real RAM
just a dime throw
This helps me immensely with my DD into the tech & companies involved in the memory sector, Thank you very much Anastasi!
Thank you! Just wanted to say you have a mistake in the figure you show (e.g. 12:38) labelling the latency of flash memory as milliseconds (1/1000s) when, as you say in the audio, the latency is in microseconds (1/1000000s)
What are the implications of photonics integration in memory?
Linked to my substack, title, "The very definition of brilliant" That meams you Anastasi. 😊
Thank you for your presentation. I found it fascinating. The phase change memory, amorphous crystal back to uniform array crystal seems like the mental models used to explain demagnetization around the currie point.
Cooling the buried cores may present a problem in the future
It's quite bizarre that you thought the PCM memory is a future replacement of SRAM, as the it has a switching speed of 40ns (on par with DRAM), according to the paper you cited. This is an order of magnitude slower than SRAM. The current only viable option to replace SRAM is SOT-MRAM, which TSMC is working on. Go research SOT-MRAM😁
It is good enough for cache application but very bad for register memory.
It also involves a physical change to the medium, which means wear and limited number of writes.
I believe a similar principle has been around since at least the 90s. I used to have a CD-R/W type device that used a laser to heat up spots of a special metallic medium, changing it from smooth to amorphous. Could be rewritten some number of times.
I will say though, your point is probably good and valid, but could have been made more constructively.
@@kazedcat its not good enough for cache, modern caches are at most in the low dozen of ns, 40ns is DRAM levels of latency
This is true. PCM is totally useless as SRAM replacement and doesn’t have sufficient speed or rewrite resilience. Honestly, she really failed to understand its use case. It’s a great alternative to floating-gate FLASH memory, not SRAM!
what about 4ds memory? 4.7 nanosecond write speeds
So each of the 2 phases of the PCM has a different resistance, so the computer can tell 1 from 0?
Can PCM memory be integrated in the same chip as the processor core? Seems like it requires a unique material to be added on a chip
loved that memory zinger, ur so awesome!
Well done excellent video and very informative 👍
Loved the graph you put together with the memory pyramid (access time vs where is used, with volatility information)!!
P.S. Your accent also becomes more and more easy to understand!
Great stuff. As someone who built their own desktops through computer conventions in the 90s I appreciate you bringing me up to date on where we stand now in personal computer development😊
In addition to learning heaps about memory, I really enjoyed hearing you say SRAM lots.
I invented stacking when I was 3.
Astro blocks.
@Sven_Dongle
Was that you!?
I though it was David!
Good job 👍😉😆
I enjoy your work.
Yups.. but it keeps bulking
Not bad. My kid at 2 would stack boxes to make a stair to get over the gate. Necessity is the mother of inventions.
Oh hey Al gore… when did u change your name? Lol
Thank you for this video. It's great. My two issues: (1) heat dissipation, is not addressed (over cycles there is growth of H.A.Z.), (2) One thing I heard about and remember vaguely, was an attempt at self healing logics (rather, materials + control circuitry), which is aimed at reducing the need for redundancy, in elements at the core of the chip (hottest and fastest environment), and attempts to also better the chip lifetime (cycles 'til dead). -I would be grateful if you could address both.
This is an excellent explanation of the current state of IC memory. Thanks.
As always fantastic work. I am not so enthusiastic right now with the new technology an endurance of 2E8 is amazing for something like storage, but the computer will go over that in no time for the cache. Even a microprocessor that is not super scalar and runs on the ghz range will be accessing memory in the other of 10^9 per second. Clearly, that access is per cell, and not for the full memory but they need to improve that number a lot.
This was an unexpected good video. This is my first video watch of the channel.
Paul Schnitzlein taught me how to design static RAM cells. This video speaks to me. Yes the set/clear, and sense amps are all in balance. It is an analogish type circuit that can burn a lot of power when being read.
Excellent analysis 👏🏾 👍🏾 👌🏾
My memory is so fragmented I can't tell which particle remembered me.
😂😂😂
@@guidedorphas10 Alterra, also included in a game I enjoyed for a very long time. SubNautica. Thanks for the extra smiles. On my face that is.
My memory is fine. Only problem is having the parity bit in a Schrödinger box.
@taurniloronar1516 damned light. Kick the box and listen for giggles. Good one.
Suggest captions. I think I’d like Anastasi in Tech even more.
Great video - thank you Anastasi :-) I think if we stack much more memory as 3rd level cache chiplets on top of CPUs we may reach the size of gigabyte 3rd level cache. And this would eliminate the external DIMMs on the mainboard which makes future Notebooks and PC again cheaper and reduces not just the complexity of the mainboard but also of the operating system, drivers and firmware because data can be loaded directly via fast PCIe lanes connected SSDs to 3rd level cache.
Stacking silicon...who woulda thought ...now it makes perfect sense for chip real estate. Thank you for your brilliant assessment of the latest chip technology. You have expanded my knowledge regularly.
Great information 😊
I remember hearing about the SRAM scalling issue some time before the Zen4 release, but then haven't heard anything even though I kept hearing about shinking nodes. Been curious what was coming of that. I was thinking that since it's not benefiting from the scaling, if it may have been counterproductive regarding degradation etc. I wonder if that is what is happening with the Intel 13 and 14K skus? I guess we will find out soon enough. Thanks for the update, I'm glad they are on top of it!
Another banger video. Do you have discord channel to reach out to?
telegram probably if shes russian
NO COPILOT! NO RECALL! This future is PRISONPLANET! NO WORK NON-STOP!
You are an amazing Vlogger and i love your accent :D
Nicely done.
I very much appreciate your videos and recommend them to every engineer I know !!
Thank you
Thanks for the updates, really informative... I was working on OTP memory designs and this new time of glass memory is looking similar to the concept of OTP memory, may be we can see this kind of evolution in OTP memories side also.
I'd love to see a AIT and High Yield collab someday :D
Great explanation
What about keeping the heat down. Sure lower power required in some case but stacking should also increase the requirement for improved cooling perhaps?
You are brilliant! Great content. Thanks for this. ;)
Thank you for sharing this new & exciting development 😊
Would be interesting to know what makes 3D stacking structure so difficult to achieve
Heat exchange maybe?
Yes, though theres more limitations, it's really hard to manage heat in a 3d structure.
It also requires new innovative ways to do it.
This is why a room temperature super conductor would be such an amazing breakthrough. You wouldn't need to worry about heat management and you could up the frequency to Thz levels while maintaining manageability even in a 3d transistor structure. Computing would be millions and billions and even trillions of times faster
Non-volatile and low-latency at the same time, coupled with scalability and hopefully cost-effectiveness in manufacturing, would be a huge technological leap. Thank you for the information.
I believe that down the line we would need to use another processor architecture than the Von Neumann one that we use today (i.e. having logic and memory separated), an architecture that instead has an "on memory compute" design, or perhaps a mix of them.
In the end the speed of light makes it hard to compute over longer distances (i.e. CM or even MM) specially when the frequency goes up and the data becomes even larger.
So basically smart RAM chips with shaders?
Interesting idea, but very speculative and in need of a demonstration at scale to assess its practicality. Moreover, although a 23% decrease in area is good for an existing bottle neck, it is not revolutionary, that would need a factor of at least 10. At the current estimated level of improvement it becomes a commercial decision on whether this improvement has a fast enough pay back to justify the r&d costs to make it practical. Is anyone making the investment to commercialize this discovery? Thank you for sharing!
Not really, the silicon lattice constant is only 0.7 nanometers. We can't scale in silicon below that. Germanium has a lattice constant of about 0.5. While process nodes and technology are mostly marketing terms and there is room for improvement beyond "1 nanometer process" - we are about at the end of what we can achieve with existing semiconductor paradigms. It will be almost all architecture and material sciences by 2030. We can't get much smaller.
A 20% improvement over SRAM is disruptive even if it doesn't scale any smaller. SRAM is unable to be scaled any smaller due to the physics underwriting operation.
We only have a few more die shrinks left before we are up against the size of the atom. ... Again, sort of ... A 1 nanometer node doesn't necessarily mean that you can make a grid of 1 nanometer square pads separated by 1 nanometer troughs on all sides, or vice-versa. But as I mentioned, the lattice constant of silicon is 0.7 nanometers, their latest process node is 1.4 nanometers. You can't really cleave off half a crystalline arrangement without having weird things happen, the next die shrink, if it is possible, would come at 0.7 nanometers. We would be, assuming we can make the grid arrangement described, making the smallest transistors possible with silicon, using existing paradigms.... And whatever paradigm comes next would need to use atoms much more efficiently - or some other concepts entirely - to function.
On the plus side, it means that in about another 10 years, we might see computers built with the idea they could last decades in their application.
@@Aim54Delta Great points! Thank you for expanding on the technological limits of the underlying physics not covered in the video. Given these fundamental limits to silicon, research efforts will move to entirely different concepts that may or may not work. Perhaps we will not see much further progress ending the decades long run of ever increasing chip performance or something new will make current silicon architectures obsolete. Fascinating field with huge commercial risk/rewards for company boards to ponder. Thank you for your comments.
@@Aim54Delta This is not true. While it is true that the Si Lattice constant is 0.7 nm, it is not true that a 1nm process node actually has features that are 1nm big. For instance, the smallest feature on a "3nm" node is around 20nm. There is plenty of room left for atleast 10 years. For instance, see IMEC's roadmap, which targets A2 (0.2nm equivalent) by 2036.
@@SomebodyHere-cm8dj
I recognized that in the original post, yet will simply respond with "I do not share their optimism."
We've built at that scale, before, and you need to redesign the device in ways that don't really gain you much. Charges at the atomic scale propagate more according to probability and the ends of an electron's wave function become a serious problem. Not only does this lead to leaking transistor gates, it leads to a form of crosstalk as you have electrons smearing their existence all over the places you don't want them.
It's similar to the ghz barrier of data busses. A 100mhz bus has a wavelength of around 2 meters, so you have about 1/4 - or 0.5 meters to play with as a mostly standard wire before you have to worry about the properties of transmission lines. By the time you reach 1Ghz, however, a full wavelength is only 22cm, and you have about 5cm before you're working with a transmission line, and that's so short that it ultimately influences every bus. There are other factors as well, stability of clock pulses, less margin for different propagation times on lines, impact of various sources of capacitance or inductance, etc - all of it compounds to make a business operating above 1GHz a completely different class of engineering and design problems not implied by the simplicity of designing a 800Mhz bus for system RAM.
Once you redesign the concept of a data bus to be a transmission line, you have a new system to scale, but it requires that paradigm shift of rethinking the wire.
Same thing with semiconductor lithography scaling.
One of the chief benefits I can see in going to optical computing is the ability to have associative addressing through polarization and muliple concurrent optical reading/writing heads for raid like processing.
thank dear, its informative
Is there any risc of read deterioration with phase change memory? Or is the change very voltage specific?
Feel free to correct me, but isn't the problem with memory scaling really more an artifact of process node naming... we haven't really been shrinking gate sizes to the extent the node names suggest for years. New process nodes are more or less just making the gates more efficient, the names are almost arbitrary. Where in the past they were linked to gate size. These improvements do allow for some better density, but mostly its improvements in current leakage. which improves power consumption and thus clock speed. Memory capacity which is nearly 1:1 linked to transistor density is just scaling at the true rate of density improvements.....
If you translate density scaling into Denard scaling which is related to the impedance of a device then what you said is somewhat true. The issue is that impedance is no longer scaling at the same rate as density. So circuits got smaller but impedance is barely moving.
What about material fatigue? How often can the state be changed? For L1 and L2 cache this had better be a very high figure.
Great video. Loved your humor and I learned so much. Thank you!
3 nm and so on is a marketing term that has no relation to any dimension of the transistors anymore. The true gate width until now is 14 nm due to asml's lithography machines limitation. The next step for the next decade is going down to 8nm (about 80 atoms wide).
This does remember me of a mechanical (robot related) movement solution.
They used the same idea in a mechanical way.
It works like muscle cells.
The BCM2837 SoC chip uses stacked RAM. The Raspberry Pi Foundation released the Pi Zero 2W in 2022 using it. So who stacked first? Regardless of who, it’s great to hear the designers are finding solutions to such huge (microscopic) problems!
Ms. Anastasia is so lovely, hard to concentrate on her narration let alone it's not easy subject to understand.😊
My concern with the phase change memory is just the lifetime and reliability. Do the cells grow oxides or change chemistry over time? Can they be ruined by ripple or electrical noise at scale that hasn't been discovered yet? Etc. Love your videos!
It should be mentioned that process node sizes like N3 or N5 nodes are density measurements and not actually a transistor size. Intel 10nm was equivalent to TSMC 7nm as they average over different area sizes and utilize different shapes and can't be compared directly or even with the size of a silicon atom which is only 0.1 nm in "size".
Awesome explanation…. Thanks 😊
I worry about using non-volatile memory for primary or cache memory because of the security aspect. If the information remains after power is interrupted, quite a few "secrets" will be in clear text, and the determined and well equipped "bad actor" will be able to extract surprising amounts of information from a system.
My industry has to issue letters of volatility with everything we produce, and for anything with NVM, the sanitization procedure usually involves removing the part with non-volatile storage and destroying it. The only exception is when it can be proven that the hardware is incapable of writing to that NVM from any component present on the assembly, even if malicious or maintenance software is loaded onto the device. This phase change memory built in the same package as the CPU logic could not be provably zeroized without some sort of non-bypassible hold up power, and that would increase the cost and size of the chip package.
I think this is very promising for secondary addressable storage, but I don't see it replacing main memory in most applications.
Love the channel!
So fancy! I think I want that laptop
I had thought of building memory (and the whole IC) in 3D 10 years ago. I think I even put the idea in my website years ago. One part of my idea that is not used yet is using microfluidics to cool the chips that are stacking transistors in 3D, thus restricting heat transfer. The channels could run many levels, and of course, they need fluid-tight connections (a big problem). And use optics to communicate instead of a BUS. Possibly LED or laser tech.
I love the way you explain the topic it gets me thinking even though I have no idea. Like possibly folding the memory and interconnecting them to form cubes cause I always see dies represented in 2d. Like I said, not my field.
Thank u for pointing this out!👍Not just on chip SRAM memory, but operating memory in general has a lot of catchup to do with the compute logic not only because of the limitation of further shrinking SRAM and demand from the AI workloads. Operating memory has been historically left behind the compute logic and in a way ignored "nature's" way of things (brain neurons) by being the same and as fast as compute/processing while having sufficient capacity. Maybe PCM or other memory technologies will deliver that in the future, however I agree with u that L1 cache will most definitely continue to use SRAM for the foreseeable future and L2/3/4 with larger capacities will most likely go first with the stacked SRAM before moving to new technology like PCM or resistive memory.
when you get close to the size of an atom, which i think is close to 0.5nm you run into problems that can not be fixed. In particular, your going to run into the problem that highly focused mental intent will interfere with the operation of the chip itself. You also can not shield this - not in a compact way.
It all works out in the end because the only reason for continuing to put more and more SRAM on chips is for AI processors. I say it all works out in the end because in roughly 5 years the AI fad will be over with because it will hit both the "human data" barrier (Generative AI needs human data to base it's model off of) and more importantly - the Power Generation bottleneck. There just isn't enough power generation capability for investors to get a ROI in say less than 10 years.
A lot of electrical grids are trying to "go green", the problem with that is they're having problems keeping the lights on as it is. With the solar flare activity and the weakening earth magnetic field we will be experiencing about 10 years of very VERY extreme weather. Summers will be hotter, winters will be colder. Meaning? We will need MORE electrical power to keep ourselves cool in the summer and more electrical power to keep ourselves from freezing to death in the winter. Texas had this probably two years ago. The temperature suddenly dipped down so low that the lubricant in the transmissions of the massive wind generators (which power most of their state) FROZE, the wind kept blowing the turbine blades and what happened? The gear boxes exploded, shredding themselves into metallic shrapnel.
The only way the Generative AI market can keep going and growing is with Nuclear Power. Problem there is that it takes 10 years to get a reactor online producing power (sometimes longer i'm told from a friend who builds them). Investors are not going to wait around for 10 years to ...probably get their ROI. They'll pull their money out, and all these AI companies that are IPOs are going to go bust.
So all of these AI processors are going to be pretty much worthless. Wonder how much gold is in them? hmmmm..
Smart and beautifull, well this is something new.
I hope you become a trend , so that our kids can stop follow brainless influencers
What about using 1T-SRAM, aka epsdram/epsram for cache's instead?