Thanks for the video! But I am confused @ 15:30 Why does ADD.D has to wait for LD to commit before writing to CDB? Hasn't the result of ADD.D already been calculated at cc 8 and ready to write to CDB at cc 9?
No the result of ADD.D begins at cc8 and writes at cdb at 11 therefore commits at 12. In the video the teacher says "has to wait for the L.D, to begin EX" and also he highlights that it follows the L.D commit stage
The architecture is dual-issue, but it does not have two integer FUs. Furthermore, the integer FU is used for effective address calculation for loads and stores. Therefore, even though DADDI can be issued in the same cycle as the preceding S.D, its execution stalls due to a structural hazard at the integer FU which is occupied with effective address calculation for the S.D.
IPC = 1/CPI not IPC = CPI-1 as on one of the later slides.
Thanks for the video!
But I am confused @ 15:30
Why does ADD.D has to wait for LD to commit before writing to CDB? Hasn't the result of ADD.D already been calculated at cc 8 and ready to write to CDB at cc 9?
No the result of ADD.D begins at cc8 and writes at cdb at 11 therefore commits at 12. In the video the teacher says "has to wait for the L.D, to begin EX" and also he highlights that it follows the L.D commit stage
DADDI need not stall for a clock cycle because it is a dual-issue superscalar and 2 instructions can be executed in one clock cycle.
The architecture is dual-issue, but it does not have two integer FUs. Furthermore, the integer FU is used for effective address calculation for loads and stores. Therefore, even though DADDI can be issued in the same cycle as the preceding S.D, its execution stalls due to a structural hazard at the integer FU which is occupied with effective address calculation for the S.D.
@@TheNewTimeNetwork Right, this is the strength of dynamically scheduled processor
Subsequent L.D can only start after DADDI broadcasts its result. Am I right?