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At the end the demonstration of mnemonics wasn’t shown on background place

Extraordinary....simple and clear....Thank you very much

Thank you for an amazing lecture.

Slides don't work 😢

Sehr gut.. Danke

The microphone is really killing this great series !

Vielen Dank!

Very good video!

Best explanation on internet! will never forget Amdahl's law

at 6:42 "The two inner loops access an N times N/B submatrix of x", I think instead he should have said "The two inner loops access an N times B submatrix of x"?

thankssss for this video

thank you for sharing knowledge selflessly!

Clear, concise, precise - what I'd expect from a German

Sir you are great but I am not understand

Thanks for much

thanks king I've got an exam tm

Amazing and simple

thanks for great explanation.

Thx Germany 🇩🇪 I need this for finals next week. From 🇺🇸

Thx Germany 🇩🇪 I need this for finals next week. From 🇺🇸

Prof. Dr. Juurlink, thank you so much for your informative and crisp videos! They are very helpful for my computer architecture course here in the U.S.!

Dankeschön!

6:35 valid only if a doesn't overlap with b or c

I don't quite understand the difference between "critical word first" and "early restart" since the cpu always has to wait for the order of words, they are essentially the same right?

Unrolling twice or three times will still have stalls if register renaming and reordering is not implemented.

Excellent class!

Is the read hit only if the block was present the the cache of the core attempting to read? or is it a hit so long as any core has it in the shared state?

thats great explanation

These videos are awesome

ahhahahahahhahahahahhaha einfach von der tub

Why did I find this course so late? Thank youuuuu! :D

great vid

Small update: automatically branch-speculative VLIW machines have been built since this video was published, such as Intel's Poulson class.

STOP WAVING YOU HANDS IT IS SO DISTRACTING I CAN'T FOCUS ON THE LESSON.

Thank you. Very clearly explained.

A bit complicated and ugly. It looks much better in masm

Awesome explanation! Just 5 mins and I've understood the concepts. Thank you a lot!

Hello professor, thanks for this series I have one question if load is not stored in load buffer due to RAW hazard will it cause subsequent load to stall as previous load op can not be stored in load buffer? Also will stall happen if load and store EA register is itself busy?

This is exactly the video I've been looking for. Thank you.

noice

if a processor can snoop w write miss from another processor waht is the utility of the invalidation signal, we can just make it automaticly invalidate a cache line whenever it snoops a write miss from another processor

Thank you very much! This lecture is super clear. You saved my final exam

GOOD VIDEO

Utecsinos, corran a ver esto

good

good vIDEO

GOOD VIDEO

Pepople hoe appear like prof or ingr to explain something must direct come to the point do not tolk to much , just the point nothing else.

Hi professor, I think there are some nosies in this video and I will some improvement in the future. Thanks for your deligent work

GOOD VIDEO!!!!