![Prof. Dr. Ben H. Juurlink](/img/default-banner.jpg)
- Видео 130
- Просмотров 1 181 474
Prof. Dr. Ben H. Juurlink
Добавлен 12 июл 2017
The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group of Technical University of Berlin (Technische Universität Berlin, TUB) investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.
www.aes.tu-berlin.de/menue/home_aes/
www.aes.tu-berlin.de/menue/home_aes/
Видео
1 2 2 MIPS64 Addressing Modes and Instruction Formats
Просмотров 8 тыс.5 лет назад
1 2 2 MIPS64 Addressing Modes and Instruction Formats
1 3 3 MIPS Pipeline Features and Pipeline Hazards
Просмотров 21 тыс.5 лет назад
1 3 3 MIPS Pipeline Features and Pipeline Hazards
Test 1 5 1 Caches and the Principle of Locality
Просмотров 1,9 тыс.5 лет назад
Test 1 5 1 Caches and the Principle of Locality
Test 1 5 2 Direct mapped Cache Organization
Просмотров 9065 лет назад
Test 1 5 2 Direct mapped Cache Organization
Test 1 5 4 Basic Cache Optimizations to Reduce Miss Rate
Просмотров 7775 лет назад
Test 1 5 4 Basic Cache Optimizations to Reduce Miss Rate
Test 1 5 5 Cache Equations for Set Associative Caches
Просмотров 4585 лет назад
Test 1 5 5 Cache Equations for Set Associative Caches
Test 1 5 6 Cache Metrics and Improving AMAT
Просмотров 2965 лет назад
Test 1 5 6 Cache Metrics and Improving AMAT
Test 1 5 7 Reduce Miss Penalty by Multilevel Cache
Просмотров 5065 лет назад
Test 1 5 7 Reduce Miss Penalty by Multilevel Cache
Test 1 5 8 Give Priority to Read Misses
Просмотров 2705 лет назад
Test 1 5 8 Give Priority to Read Misses
Test 2 3 2 SIMD Register File, Data Types, and Instructions
Просмотров 4085 лет назад
Test 2 3 2 SIMD Register File, Data Types, and Instructions
Test 2 3 3 SIMD Multiplication Instructions
Просмотров 2845 лет назад
Test 2 3 3 SIMD Multiplication Instructions
Test 2 3 4 Special Purpose Instructions & Data Conversions
Просмотров 1645 лет назад
Test 2 3 4 Special Purpose Instructions & Data Conversions
Test 2 3 5 Data Alignment and Reordering
Просмотров 2595 лет назад
Test 2 3 5 Data Alignment and Reordering
Test 2 4 1 TLP Motivation and Introduction
Просмотров 2305 лет назад
Test 2 4 1 TLP Motivation and Introduction
Test 2 4 3 Introduction to Block Multithreading
Просмотров 1055 лет назад
Test 2 4 3 Introduction to Block Multithreading
Test 2 4 5 Introduction to Interleaved Multithreading
Просмотров 1085 лет назад
Test 2 4 5 Introduction to Interleaved Multithreading
Test 2 4 6 Examples of Interleaved Multithreading
Просмотров 845 лет назад
Test 2 4 6 Examples of Interleaved Multithreading
Test 2 4 7 Introduction to Simultaneous Multithreading
Просмотров 2125 лет назад
Test 2 4 7 Introduction to Simultaneous Multithreading
Test 2 4 8 Examples of Simultaneous Multithreading
Просмотров 1325 лет назад
Test 2 4 8 Examples of Simultaneous Multithreading
1 3 8 Scheduling Instructions for Branch Delay Slot
Просмотров 16 тыс.5 лет назад
1 3 8 Scheduling Instructions for Branch Delay Slot
At the end the demonstration of mnemonics wasn’t shown on background place
Extraordinary....simple and clear....Thank you very much
Thank you for an amazing lecture.
Slides don't work 😢
Sehr gut.. Danke
The microphone is really killing this great series !
Vielen Dank!
Very good video!
Best explanation on internet! will never forget Amdahl's law
at 6:42 "The two inner loops access an N times N/B submatrix of x", I think instead he should have said "The two inner loops access an N times B submatrix of x"?
thankssss for this video
thank you for sharing knowledge selflessly!
Clear, concise, precise - what I'd expect from a German
Sir you are great but I am not understand
Thanks for much
thanks king I've got an exam tm
Amazing and simple
thanks for great explanation.
Thx Germany 🇩🇪 I need this for finals next week. From 🇺🇸
Thx Germany 🇩🇪 I need this for finals next week. From 🇺🇸
Prof. Dr. Juurlink, thank you so much for your informative and crisp videos! They are very helpful for my computer architecture course here in the U.S.!
Dankeschön!
6:35 valid only if a doesn't overlap with b or c
I don't quite understand the difference between "critical word first" and "early restart" since the cpu always has to wait for the order of words, they are essentially the same right?
Unrolling twice or three times will still have stalls if register renaming and reordering is not implemented.
Excellent class!
Is the read hit only if the block was present the the cache of the core attempting to read? or is it a hit so long as any core has it in the shared state?
I don't know what are you asking by 'read hit' but assuming you mean cache hit, data must be in that processor's cache. If not then that processor demands it from the bus and makes it clear that it intends to modifi it so that the bus can invalidate other processor's cache data and supply the data to modifying processor's cache
thats great explanation
These videos are awesome
ahhahahahahhahahahahhaha einfach von der tub
Why did I find this course so late? Thank youuuuu! :D
great vid
Small update: automatically branch-speculative VLIW machines have been built since this video was published, such as Intel's Poulson class.
STOP WAVING YOU HANDS IT IS SO DISTRACTING I CAN'T FOCUS ON THE LESSON.
So true bro it is totally not necessary
Thank you. Very clearly explained.
A bit complicated and ugly. It looks much better in masm
Awesome explanation! Just 5 mins and I've understood the concepts. Thank you a lot!
Hello professor, thanks for this series I have one question if load is not stored in load buffer due to RAW hazard will it cause subsequent load to stall as previous load op can not be stored in load buffer? Also will stall happen if load and store EA register is itself busy?
This is exactly the video I've been looking for. Thank you.
noice
if a processor can snoop w write miss from another processor waht is the utility of the invalidation signal, we can just make it automaticly invalidate a cache line whenever it snoops a write miss from another processor
Thank you very much! This lecture is super clear. You saved my final exam
GOOD VIDEO
Utecsinos, corran a ver esto
good
good vIDEO
GOOD VIDEO
Pepople hoe appear like prof or ingr to explain something must direct come to the point do not tolk to much , just the point nothing else.
Hi professor, I think there are some nosies in this video and I will some improvement in the future. Thanks for your deligent work
GOOD VIDEO!!!!