Tomasulo's Algorithm example| lec 54| Advanced computer architecture| BhanuPriya

This video explains about Tomasulo's Algorithm example
This video is contributed by Bhanupriya.
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[@vihanmewari7624]

You really explained well....I can relate your efforts as I am also a faculty....Superb Efforts

[@allaboutcsit]

Thank you, please subscribe my channel for more information

[@steventran4231]

I believe there is an error that you didn't address and that's for the DIV instruction.
You divide the F8,F2 when it should be F0 and F6

[@deepashri731]

Yess

[@ML-xp1kp]

At 21:35, there is an unexplained 1-cycle latency between SUB and ADD. The events that happen before cycle 9 imply that there is 0 latency between a command entering WB stage and another dependent command entering the X stage.

[@Simply_Shubho]

same doubt... is it correct to give 1 latency?

[@samuelcortez3401]

This is incredibly helpful. After understanding the background of Tomasulo's algorithm, this step-by-step presentation really helped me grasp the algorithm even more. I'm not sure if it was ever explained in this video, but are the values you placed in Qj and Qk called tagx? I'm referring to Qj = "Load1", for example. My understanding is that "Load1" is the tag/name of the Load1 buffer.

[@tgm6540]

Mam,Please describe about traveling salesman problem using branch and bound method.

[@stosic8996]

You have RAW hazard between ADD2 and DIV, you are not able to WR ADD2 in 11th cycle since you need the value from LOAD1 to divide in DIV F10. Failed.

[@redhikdileep5130]

I think you have given wrong value to F10 in Result Status

[@krishnatr7221]

mam cant we start multiplication at 4th cycle itself...rather than 6th cycle??

[@mahnoor3769]

no we cant because we dont have f2 which is result of load 2 but source of multiply1 the second load is not completed yet so when f2 WB in 5 cycle so starts from 6 cycle

[@uvarajupdates4464]

At clock cycle 5 , shouldnt we write div into result status register?

[@PriyamSheth]

Ma'am, how can we change the value of F6 in add instruction as it is read in the previous instruction by DIV. We have WAR data hazard, so the value will be changed before it is read. Can you please explain this one?

[@VishalKumar-lk1vf]

You are right it will be both div and add will write back at 57 cycle

[@pramitreus5599]

You the best.

[@allaboutcsit]

Thank you 😊

[@denishishere8501]

Mam, really a life saver video.....awesome explanation

[@allaboutcsit]

Thank you 😊, please subscribe and share my channel

[@pritishpattnaik4674]

very confusing

[@allaboutcsit]

Yes topic itself is a little bit confusion, but don't leave it, try to watch twice or thrice, take paper and pen and try to solve step by step by watching video

[@pritishpattnaik4674]

@@allaboutcsit yes mam , but u explained it nicely

[@bogdanpetkovic4044]

ok

[@animeshdhara3735]

Very nice explanation

[@allaboutcsit]

Thank you 😊

[@plasteredpeak]

Queen

[@allaboutcsit]

Thank you