z790 avx offset 0 bug workaround I have noticed that AVX offset issue mentioned by you in one of your videos has simple but inconvenient workaround on Gigabyte motherboard. On my 14700kf 56/44/50 HT OFF / Z790 Gaming X AX, AVX small tests (P95/OCCT) downclocks from 5.6 to 5.5 with AVX offset 0 ONLY at 1st boot of PC from full power off state, if I restart PC at least once then AVX is NOT downclocking from 5.6 under any load, even prime 95 small avx until next power off. Unleashed bios profile shows the same behaviour so I am using intel performance profile + manual settings: cep ON, 400icc, 350w, 1.45vr, 1.35v vcore, AC45/DC55, LLC HIGH, cpu allways holds max clocks and temps are never higer than 85°C. config: GPU: RTX 3090 OC / Alphacool Aurora water block / liquid metal CPU: i7 14700kf OC HT OFF 56/44/50/ delided / liquid metal RAM: Corsair Vengeance 2x 16GB DDR 7000 CL34 (tightened timings) PSU: Corsair HX1500i CASE: Corsair 7000D CPU WATER BLOCK: Thermal Grizzly Mycro Direct Die Pro V1 RADIATORS : 2 x Corsair XR5 420mm / 30mm FANS inside case: 7x Noctua NF-A14 FANS outside of case: 2x Noctua NF-A20 PUMPS: Corsair XD5 and EK Inertia D5 Coolant: Mayhems XT 1 NVME SSDs: 1x 2TB PCIE 4.0 SN850x and 2x SN850x 1TB in RAID 0 MOTHERBOARD: Gigabyte z790 gaming X AX sorry for off topic 😉
tCWL is essentially the time it takes for the memory to prepare for receipt of the data from the memory controller. That is for the I/O buffers to synchronise, write drivers to get ready, and the sense amlifiers to switch to write mode.
This is amazing. Much needed content. Gives enough info that you aren't just stumbling around in the dark without devolving into engineer technobabble that you need to already understand the subject to understand. Much appreciated.
You're the man for this some kind of things. Watched a lot of your videos to learn more about the behauviour of RAM memory chips (basicly the memory controller) and there timings. 💪
When I set tRC and tRAS too tight, I "saw" recoverable iGPU errors for me on the 9800x3d. Basically random flashes of green or black. It was interesting cause it wasn't tripping y-cruncher, even though I could see the screen flickering randomly. Supposedly because y-cruncher is always trying to do something "useful" at-least until the user or a periodic process forces the CPU to interrupt itself, then you get those faults that occur late in a test. To me, this family of timings (tRP+tRAS=tRC) has to do with optimizing interrupt and speculative execution performance, which is probably not all that uncommon with some applications like VMs and external IO. Its going to depend on things we can't control, hence stability. I wonder if Karhu or TM5 tests deliberately do something to watch for these being too tight. AMD has done us no favors with some of this terminology. I do wonder if we will get CPUs or computations that will care about tWRWRSCL. These thoughts and discussions have helped me greatly with understanding how to successfully tighten the 48x2 DR Hynix kit I have. I think I need to loosen some things for robustness.... It's almost done and I'm very excited.
When I choose Expo 1 or 2 or Expo Tweeked, I get the same speed and same timing, and there is no difference between them. CPU RYZEN 7 7800X3D RAM LEXAR ARES 6400 32GB MOTHERBOARD ASUS PRIME X870-P WIFI
Those are proprietary ideas from ASUS. Basically masks for each timing to pull it from the DIMM/EXPO/SPD or from the BIOS' DB/algorithm. They are starting points, and they might be the same, or the differences haven't been found, or BZ's content will enable you to set better timings then any of the above ASUSisums.
BL missing :) Data transfer itself also take time. To understand better why we can't lower some delays significantly lower. We're actually already dealing with lightspeed measurements, and you can't go faster than light. ruclips.net/video/IaXdSGkh8Ww/видео.html
if by BL you mean burst length. It's locked at 8 cycles. So I don't really consider it a timing since it's just a fundamental rule of how DDR5 functions. Also it's it's mentioned in the video. So congrats on not watching it/not paying attention.
This reminds me I'm on an old bios for my motherboard (bios 1709 from late 2023) on the Asus x670e hero with good 6000 ram overclock to 6400mt/s. I'm hesitant to update bios concerned my setup wont be stable anymore. Is that a valid concern or will it likely be the reverse in that newer bioses make things even more stable?
Nice video 😀. Now explain why DDR5 ECC has 2 extra chips per 8 chips and still has total width of 72 bits same as DDR4 that has 1 extra chip per 8 chips. I was looking at dmidecode right now. 2x48GB ECC DDR5. And you don’t need a server platform. Regular X870 motherboard will do. 😀
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Kinda want to re-record this and I don't even know why. Not like anything would really change.
Madman
z790 avx offset 0 bug workaround
I have noticed that AVX offset issue mentioned by you in one of your videos has simple but inconvenient workaround on Gigabyte motherboard.
On my 14700kf 56/44/50 HT OFF / Z790 Gaming X AX, AVX small tests (P95/OCCT) downclocks from 5.6 to 5.5 with AVX offset 0 ONLY at 1st boot of PC from full power off state, if I restart PC at least once then AVX is NOT downclocking from 5.6 under any load, even prime 95 small avx until next power off.
Unleashed bios profile shows the same behaviour so I am using intel performance profile + manual settings:
cep ON, 400icc, 350w, 1.45vr, 1.35v vcore, AC45/DC55, LLC HIGH, cpu allways holds max clocks and temps are never higer than 85°C.
config:
GPU: RTX 3090 OC / Alphacool Aurora water block / liquid metal
CPU: i7 14700kf OC HT OFF 56/44/50/ delided / liquid metal
RAM: Corsair Vengeance 2x 16GB DDR 7000 CL34 (tightened timings)
PSU: Corsair HX1500i
CASE: Corsair 7000D
CPU WATER BLOCK: Thermal Grizzly Mycro Direct Die Pro V1
RADIATORS : 2 x Corsair XR5 420mm / 30mm
FANS inside case: 7x Noctua NF-A14
FANS outside of case: 2x Noctua NF-A20
PUMPS: Corsair XD5 and EK Inertia D5
Coolant: Mayhems XT 1
NVME SSDs: 1x 2TB PCIE 4.0 SN850x and 2x SN850x 1TB in RAID 0
MOTHERBOARD: Gigabyte z790 gaming X
AX
sorry for off topic 😉
Do it and keep both up
Maybe the reason you want to rerecord this is because you didn't fully understand a number of the timings?
tCWL is essentially the time it takes for the memory to prepare for receipt of the data from the memory controller. That is for the I/O buffers to synchronise, write drivers to get ready, and the sense amlifiers to switch to write mode.
Really loves your ddr4 series. Thanks for the upload. Youre the man
@@lumivar1719 you could almost say, he’s the RAM. Thank you for coming to my show I’ll see myself out now
This is amazing. Much needed content. Gives enough info that you aren't just stumbling around in the dark without devolving into engineer technobabble that you need to already understand the subject to understand. Much appreciated.
Very much appreciated.
You're the man for this some kind of things. Watched a lot of your videos to learn more about the behauviour of RAM memory chips (basicly the memory controller) and there timings. 💪
Thank you ive wanted to learn more about this but have struggled finding somehting that didnt make me fall asleep :)
I strugle to find words to show my gratitude. Thank you, this will help immensely.
the goat has returned
this video is the biggest blessing
You’re the man!
Would DDR4 timings with the same name effectively function in the same way?
they do. DDR5 is basically just DDR4 with more bank groups and a longer burst length
GOATed Video
Love to see OC isnt dead, at least we have mem oc,thank you for the content 💪🫡
insane 1 hour of essential hidden knowledge for mortals
Thank you for your service
Nice, thanks BZ.
Very informative as always. Also, I don't know if you are interested but I'd love to see some Arrow Lake testing.
When I set tRC and tRAS too tight, I "saw" recoverable iGPU errors for me on the 9800x3d. Basically random flashes of green or black. It was interesting cause it wasn't tripping y-cruncher, even though I could see the screen flickering randomly. Supposedly because y-cruncher is always trying to do something "useful" at-least until the user or a periodic process forces the CPU to interrupt itself, then you get those faults that occur late in a test. To me, this family of timings (tRP+tRAS=tRC) has to do with optimizing interrupt and speculative execution performance, which is probably not all that uncommon with some applications like VMs and external IO. Its going to depend on things we can't control, hence stability. I wonder if Karhu or TM5 tests deliberately do something to watch for these being too tight.
AMD has done us no favors with some of this terminology. I do wonder if we will get CPUs or computations that will care about tWRWRSCL. These thoughts and discussions have helped me greatly with understanding how to successfully tighten the 48x2 DR Hynix kit I have. I think I need to loosen some things for robustness.... It's almost done and I'm very excited.
This is EPIC. Thanks!
Could be a cool project to do an animated diagram that goes at 1Hz where you can change the timings of things and see how they misalign.
This is gold❤
I've save this video for tonight to fall asleep to.
Thank you sir.
When I choose Expo 1 or 2 or Expo Tweeked, I get the same speed and same timing, and there is no difference between them.
CPU RYZEN 7 7800X3D
RAM LEXAR ARES 6400 32GB
MOTHERBOARD ASUS PRIME X870-P WIFI
Those are proprietary ideas from ASUS. Basically masks for each timing to pull it from the DIMM/EXPO/SPD or from the BIOS' DB/algorithm. They are starting points, and they might be the same, or the differences haven't been found, or BZ's content will enable you to set better timings then any of the above ASUSisums.
Why does virtualization based security lowers BUS speed to 98Hz instead of keeping it at 100Hz?
BL missing :) Data transfer itself also take time.
To understand better why we can't lower some delays significantly lower. We're actually already dealing with lightspeed measurements, and you can't go faster than light.
ruclips.net/video/IaXdSGkh8Ww/видео.html
if by BL you mean burst length. It's locked at 8 cycles. So I don't really consider it a timing since it's just a fundamental rule of how DDR5 functions.
Also it's it's mentioned in the video. So congrats on not watching it/not paying attention.
This reminds me I'm on an old bios for my motherboard (bios 1709 from late 2023) on the Asus x670e hero with good 6000 ram overclock to 6400mt/s. I'm hesitant to update bios concerned my setup wont be stable anymore. Is that a valid concern or will it likely be the reverse in that newer bioses make things even more stable?
thank you
i think a micron ddr5 video would we awesome, not really a lot of info on micron ics floating a out
Nice!!
CONTENT
I just Googled it yesterday wow
Asus released the apex for AMD!!!
Especially for all of us that love suffering 🎉
Godsend
Nice video 😀. Now explain why DDR5 ECC has 2 extra chips per 8 chips and still has total width of 72 bits same as DDR4 that has 1 extra chip per 8 chips. I was looking at dmidecode right now. 2x48GB ECC DDR5. And you don’t need a server platform. Regular X870 motherboard will do. 😀
pogggggggg
Bigger number better, got it.
Will purchase the ram with the highest numbers in all of them, easy as that /s
I love you man. (Not in a gay way)
U forgot to explain TLDR timings.
Foist again happy new year
Can you just come over to my house and tweak my RAM?
+1 you should go to this guy's house and tweak his ram
Second
did you manage to pre order the b850 gigabyte ai top board?. it looks amazing.
I don't do pre-orders. But once it's in stock I'm buying one as soon as I'm done with all the other stuff I'm not finished with yet