Signoff order in Physical Design | Various signoff in VLSI | Signoff Checks

[@kshubham1]

I am looking forward to have a indepth tutorial on signoff 😊

[@Akk-ei9uw]

Do we do IR analysis in schematic or layout

[@happyminds3418]

make more videos related to signoff

[@TeamVLSI]

Sure, will try to cover the topic in details soon.

[@mallikarjunts325]

Thanks

[@TeamVLSI]

Welcome Mallikarjun.

[@svnprakash5734]

Constraints of LDO and babdgap please sir 🙏🙏🙏

[@sanjayganesh2079]

Hi Sir
Please upload a video how to fix manually shorts and opens in icc2 or fusion complier.

[@TeamVLSI]

Hi Sanjay, sure will try to cover that.

[@UzairKhan-ug4hy]

Kindly sir make lab tutorial on each sign-off checks that how to check or do this checks in Genus and innvous

[@TeamVLSI]

Hi Uzair,
Sure, will try to make soon.

[@jagruthgowda3006]

What RV team will do ?

[@TeamVLSI]

Hi Jagruth,
Basically, IR EM cleans up.

[@jagruthgowda3006]

Thank you sir

[@svnprakash5734]

Sir please upload input and output files for
Running LVS and DRC please
(If we want to run LVS, DRC we have to give files, I what that files) please I have interview this week please upload as soon as possible