As you said after applying MCP for setup after 4 clk cycles ,hold will be checked at before that clk cycle But hold will be checked at same Clk edge and that are both different edges pls clarify my doubt
Sir.. can you tell... How we will get know about MCP. Is there any command to check what are the MCP in our design..(consider we didn't set MCP in sdc fie)
Hold constraint is basically trying to prevent a race condition so that a fast data doesn't accidentally pass through to the capture flop at the same clock edge, so hold check is only relative to a clock edge. Setup constraint is trying to prevent a scenario where data moves so slowly that it doesn't get to the capture flop even before the NEXT clock edge, so it needs to take the entire clock cycle into consideration.
While writing for MCP for hold you told 3 that Is (n-1) and in note you are telling applying MCP for setup hold gets affected by same no of cycles in Same direction pls correct me if I am wrong
can you please check once where will use -start and -end switch? I think in slow to fast we use -end switch and in fast to slow clock we use -start switch....please let me know also if I am wrong
Thanks, Kavita. You are right. The way you are saying will always shift the check edge with respect to the shorter clock period, Which is absolutely right. But I don't think it is a necessary condition.
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Hi Team VLSI, can you do one video on Half Cycle Path?
Nice Arun ... Keep continue this series on short topics ... Thanks
Sure 👍
Nice presentation
Thanks a lot Arun. Keep supporting!
As you said after applying MCP for setup after 4 clk cycles ,hold will be checked at before that clk cycle
But hold will be checked at same Clk edge and that are both different edges pls clarify my doubt
time stamp please.
Sir.. can you tell...
How we will get know about MCP. Is there any command to check what are the MCP in our design..(consider we didn't set MCP in sdc fie)
sir you have written start in the command and making changes in the end clock in the final example please check it. If i am wrong let me know
Why setup check is done at next clock edge and hold at the same edge?
Setup always affects the capture flop and hold affects the launch flop
Hold constraint is basically trying to prevent a race condition so that a fast data doesn't accidentally pass through to the capture flop at the same clock edge, so hold check is only relative to a clock edge. Setup constraint is trying to prevent a scenario where data moves so slowly that it doesn't get to the capture flop even before the NEXT clock edge, so it needs to take the entire clock cycle into consideration.
While writing for MCP for hold you told 3 that Is (n-1) and in note you are telling applying MCP for setup hold gets affected by same no of cycles in Same direction pls correct me if I am wrong
time stamp pls of video.
@@TeamVLSI at 15:23
If I have a hold violation of 100ps how much setup slack I need.
Hi Aneel,
Generally 2 to 3 times depending on library.
@@TeamVLSIHI could you please make a video on why do we need virtual clocks
How multicycle will help to fix hold time
Hi Arun,
It wont help.
can you please check once where will use -start and -end switch? I think in slow to fast we use -end switch and in fast to slow clock we use -start switch....please let me know also if I am wrong
Thanks, Kavita. You are right.
The way you are saying will always shift the check edge with respect to the shorter clock period, Which is absolutely right. But I don't think it is a necessary condition.
grt work
Thanks Arjun. Keep learning keep supporting...
@@TeamVLSI bro..can u do for rtl.spec..like coding constraint, linting
Why hold is reverting back after applying MCP?
Hi Jagdeesh,
Because we want to provide MCP only for setup.
How to identify multi cycle paths in design?
It is an exception, you can check the SDC file.
@@TeamVLSI If it is not there in SDC and then how to identify violation is true or false due to multicycle
Check for flip flops which are driven by clocks of different frequencies.