Synchronous Counter| Part 2 | Down Counter using JK | Up-Down Counter | KTU | CST203 ECT203 ITT203 |
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- Опубликовано: 12 дек 2020
- Syllabus Common to :
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY (KTU)
(REGULATION 2019)
1)CST203 Logic System Design ( COMPUTER SCIENCE ENGINEERING)
2)ECT203 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
3)EET206 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
4)ITT203 Logic System Design (INFORMATION TECHNOLOGY)
5)EBT205 Logic Circuit and Design (BIOMEDICAL ENGINEERING)
6)ICT203 Design of Logic Circuits (INSTRUMENTATION AND CONTROL ENGINEERING)
7)ECT203 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING)
(REGULATION 2015)
1)CS203 Switching Theory and Logic Design (COMPUTER SCIENCE ENGINEERING)
2)IT201 Logic System Design (INFORMATION TECHNOLOGY)
3)EC207 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
4)EE204 Digital Electronics and Logic Design (ELECTRICAL AND ELECTRONICS ENGINEERING)
5)EC207 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING AND INSTRUMENTATION)
6)IC207 Design of Logic Circuit (BIOMEDICAL ENGINEERING)
COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
1) Master of Computer Applications (MCA)
20-381-0103 Digital Electronics and Computer Organization
2)EC-15-1304 Digital Electronics (BTECH ELECTRONICS AND COMMUNICATION ENGINEERING)
3)CS-14-1302 & 19-202-0302 Logic Design (BTECH COMPUTER SCIENCE ENGINEERING)
4)EE-15-1405 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
KERALA POLYTECHNIC DIPLOMA (SITTR KERALA)
1) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS ENGINEERING)
2) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS AND COMMUNICATION ENGINEERING)
ANNA UNIVERSITY ( REGULATION 2017)
1)EC8392 Digital Electronics (BE ELECTRONICS AND COMMUNICATION ENGINEERING)
2)EE8391 Digital Logic Circuits (BE ELECTRICAL AND ELECTRONICS ENGINEERING)
3)EE8351 Digital Logic Circuit (BE ELECTRONICS AND INSTRUMENTATION ENGINEERING)
4)CS8351 Digital Principles and System Design (BE COMPUTER SCIENCE ENGINEERING)
5)CS8351 Digital Principles and System Design (BE INFORMATION AND TECHNOLOGY)
Way better than college lectures
ഞാൻ തെറ്റി എന്ന് വിചാരിച്ചു check cheythu kondirikkanuyirunnu k map updown mistake und.. Baaki ellam ushar video 😍 തെറ്റിയത് മനസ്സിലായത് first ലെ video ഉള്ളത് കൊണ്ടാണ് 😃😃
Great sir👏👏
Super class
Sir, ECT 203 de playlist il ee vdo add aakittu illa😕
Well explained lectures, Thank you sir💖
Sir,
Should we always take M=0 as up counter and M=1 as down counter. can it be taken as the other way around ?
Up down counter lu t1= m EXOR Q0 kodthude sir.. Apo gates kuraykamalo.. Oru XOR matram matyallo.. Angne chythude? 🤔
can we use xor gate for T2 and T1
Sir down counter varumbozhane nammal Q3,Q2,Q1 edukune Q1,Q2,Q3 in pakaram (order)
23:55
asynchronous nn parayumbo clock ingne allalo koduka
oroninte output alle aduthek koduka
then why like this
mistake?
Ithu synchronous counter example alle !!! typing mistake aanu
Next statil 111 kayinjal 110 alla varandath (1) Downcounter alla
Up counter video link idamo plz..
Sir, fliflops inte order important aano sir when drawing counter...? T FF use cheyumbo, FF order will be T1T2T3 pakshe ivde JK FF use cheytheppo, JK3JK2JK1 order aarnu.... Ath thirichum marechum ittal difference undo? Mark kureykuvo?
Same doubt here..
Order important ahno
Up down synchronous alle , heading?
design a counter with repeated bin seqnc.. 0,1,2,4,6. how it ill b answered?is it a ring counter?
use 3 bit synchronous counter and follow the same steps.
Sir kmap varachrkuna correct anoo ??
Sir avide excitation tablil T1 and T2 yil m7=1 undaloo but sir kmapil m7 mark cheythilalo sir athu onnu explain cheyamo
00:20 il edutha kmap wrong ahnu … T2 and T1 values wrong ahnu (T2 cheythapo kittiyathu Q1Q0 ahnu ) ?
SIR..
synchronous up down counter ill
kmap thettalle..
final answer correct anu..
but kmap thettalle
K map mQ2 Q1Q0 alla..
Q1Q0 mQ2 , ee order ilaan varika , anganeyenkil sir varacha k map crrct aakum
@@mufee.0 appo eniku oru doubt table nte order l allee k-map draw cheyya ,Q1Q0 mQ2 enna order edutha table um change cheyyanoo????
Sir can i get ur notes
Up down counter kmap thettan, pls dont follow that..... 👍bakki okke nice ann🙌✨
Yes, doubt thonni comments nokki 😅
Chummatth alla 🫥
Ok da👀
Okdaaa
Quick Aayit cheyda video aanu ☺️ Aarenkilum work out cheydu nokkiyittundenkil post your final output values
State diagram and excitation tableil 000 vechu thodangiyal kozhapam indo in 1st qn
No issues !!!
Sir flipflop order importance indo
Sir k map explain cheyaamo
Synchronous up down counter
Ok sure
sir sychrinize
updownll kmap manasilayilla
Sorry for the trouble faced !!!
athil cheriya mistake und. eq correct ahh but mapping cheyathu maari poye
Nammude choice alle t vach cheyano atho jk vach cheyano enn, atho question ill parayuoo eth vach cheyanam enn
Nammude Choice aanu !!! You can choose T FF by default !!
Sir bcd synchronous counter using t flip flop solution idaavo?
Okay ! Work out cheydu nokkatte
Sir mealay and Moore machine s idaaamo???
Based on Which Syllabus ?
@@ShastraTechnicalInstitute BMT203
How to make it for 4 bit ??
As usual !! 3 bit cheyda pole thanne
Synchronous up down counter le k map thettano
athe nikum thonni
No
@@sreeharip2002.
Sir , flip flop conversions idamo.....
Yes
I will try !!
Kmap in 20.47...after solving T1= Q2Q1'+Q2'Q1 alle vara?...pls check
yaa same doubt..arelum ee doubt chodichitundo enn comment nokuvayirunu..
thaan min terms fill cheyyunna order onnu nokk. (0,1,3,2....)
@@SAVIYOTHERATTIL athoke correct aanu
enikum anganeya kittyee
vdoil ulla kmap ozhivakki table vach t1 kmap undakkiyal sir parayunna ans thanne aan kittunne
24:03 question Asynchrounous aan .. but common clock aan koduthath
Nale lsd exm ahn ale🌚
Athe ath wrng ah...common clock alla varande
Alla asynchronous counter alelum process igane alello..athinu munne crt ayit syscrons ahnenn parajitund...last partil qn mari poyatha
i think the kmap for t2 is wrong
Expression sheriyale
Wrong annen enikum thonunu
wrong anenn thonnunnu, 3,7,8,12 alle verande?
boolean expression wrong alle sir??
ahdaaaaaaaaaaaaaaaaa